E3 231 (JAN) 2:1 Digital Systems Design with FPGAs
Introduction to Digital design; Hierarchical design, controller (FSM), case study, FSM issues, timing issues, pipelining, resource sharing, metastability, synchronization, MTBF Analysis, setup/hold time of various types of flip-flops, synchronization between multiple clock domains, reset recovery, proper resets. VHDL: different models, simulation cycles, process, concurrent and sequential statements, loops, delay models, library, packages, functions, procedures, coding for synthesis, test bench. FPGA: logic block and routing architecture, design methodology, special resources, Virtex-II, Stratix architectures, programming FPGA, constraints, STA, timing closure, case study.
E3 245 (AUG) 2:1 Processor System Design
Introduction: Basic Processor Architecture, Instruction Set Design, Datapath and Controller, Timing, Pipelining. CISC Processor Design: Architecture, hardware flowchart, the implementation from flowchart, exception, control store, microcode design. RISC Processor Design: single cycle implementation, multi-cycle implementation, pipelined implementation, exception, and hazards handling, RISC-V. Memory Hierarchy: Cache, Paging, TLB. Bus: Bus Topologies, AXI, Bus Bridges, BFM, Network-on-Chip. Superscalar Processors Design: Superscalar organization, superscalar pipeline overview, VLSI implementation of dynamic pipelines, register renaming, reservation station, re-ordering buffers, branch predictor, and dynamic instruction scheduler, etc.
NPTEL Video Course: Digital System Design with PLDs and FPGAs
- Gokulan T, Akshay Muraleedharan, and Kuruvilla Varghese, “Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA” Euromicro Conference on Digital System Design (DSD) 2020, Virtual Event, 26-28 August 2020, pp. 340-343, DOI: 10.1109/DSD51259.2020.00062
- A. Birari, P. Birla, K. Varghese and A. Bharadwaj, “A RISC-V ISA Compatible Processor IP,” 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, 2020, pp. 1-6, DOI: 10.1109/VDAT50263.2020.9190558
- Nimish Shah, Paragkumar Chaudhari, and Kuruvilla Varghese, “Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network”, IEEE Transactions on Neural Networks and Learning Systems, Volume 29, Issue 12, pp. 5922-5934, December 2018, DOI: 10.1109/TNNLS.2018.2815085
- Sajna Remi Clere, Sachin Sethumadhavan, Kuruvilla Varghese, “FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training”, 2018 21st Euromicro Conference on Digital System Design (DSD), Prague, Czech Republic, August 2018, pp. 381-388, DOI: 10.1109/DSD.2018.00072
- Suseela Budi, Pradeep Gupta, Kuruvilla Varghese, Amrutur Bharadwaj, “A RISC-V ISA Compatible Processor IP for SoC”, 2018 International Symposium on Devices, Circuits and Systems (ISDCS), Indian Institute of Engineering Science and Technology, Shibpur, March 29-31 2018, pp. 1-5, Kolkata, India. DOI: 10.1109/ISDCS.2018.8379629
- A. Dey, S. Jose, K. Varghese and S. G. Srinivasa, “A High-throughput Clock-less Architecture for Soft-Output Viterbi Detection”, 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, USA, Aug. 2017, pp. 779-782, DOI: 10.1109/MWSCAS.2017.8053039
- Kavya Sharat, Sumeet Bandishte, Kuruvilla Varghese, Amrutur Bharadwaj, “A Custom Designed RISC-V ISA Compatible Processor for SoC”, 21st International Symposium on VLSI Design and Test (VDAT-2017), 29 June – 2 July 2017, IIT Roorkee, India, 29 June – 2 July 2017, Communications in Computer and Information Science, vol 711. Springer, Singapore, pp. 570-577, DOI: https://doi.org/10.1007/978-981-10-7470-7_55
- Pradeep Gupta, Suseela Budi, Kuruvilla Varghese, and Amrutur Bhardwaj, “A RISC-V Compatible Processor Ip for SoC”, RISC-V International Conference, April 2017, IIT Madras, Chennai.
- Siddhartha B. Rai, Srinidhi M.S., Kuruvilla Varghese, and Srividhya R “Flow Control for Onboard Solid State Recorder” 4th International Conference on Electronics and Communication Systems, 24-25 Feb 2017, Coimbatore, India, pp. 65-69
- Saugata Datta, Kuruvilla Varghese, and Shayan Srinivasa, “A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA”, 29th International Conference on VLSI Design (VLSID 2016), January 4-8, Kolkata, pp. 439-444.
- Anant Devi, Maulik Gandhi, Kuruvilla Varghese, and Dipanjan Gope, “Accelerating method of moments based package-board 3D parasitic extraction using FPGA” Microwave and Optical Technology Letters, Volume 58, Issue 4, pp. 776-783, April 2016
- Sriram Venkateshan, Alap Patel, and Kuruvilla Varghese, “Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 10, pp. 2221-2232, Oct. 2015
- Anant Devi, Maulik Gandhi, Kuruvilla Varghese, and Dipanjan Gope, “Hardware Accelerator for 3D Method of Moments based Parasitic Extraction”, The 2013 IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) symposium, December 2013, Nara, Japan. pp. 100-103
- Karthikeyan P, Srijith Haridas, and Kuruvilla Varghese, “Transparent FPGA based Device for SQL DDoS Mitigation” International Conference on Field-Programmable Technology 2013 (ICFTP 2013), December 2013, Kyoto, Japan. pp. 82-89
- Jimit Shah, K.S. Raghunandan, and Kuruvilla Varghese, “HD Resolution Intra Prediction Architecture for H.264 Decoder” 25th IEEE International Conference on VLSI Design VLSID 2012, January 2012, Hyderabad, India. pp.107 – 112
- Tejasvi Anand, Yagnesh Waghela, and Kuruvilla Varghese “A Scalable Network Port Scan Detection System on FPGA” IEEE International Conference on Field-Programmable Technology (FPT’11). December 2011, New Delhi, India. pp. 1-6
- Gandhi Arpit, Raghavendra Adiga and Kuruvilla Varghese, “Space Efficient Diagonal Linear Space Sequence Alignment” 10th IEEE International Conference on Bioinformatics and Bioengineering (BIBE 2010) 3 June 2010, Philadelphia, pp. 244-249
- Vrishali Vijay Nimbalkar, and Kuruvilla Varghese, ” In-Channel Flow Control Scheme for Network-on-Chip” 16th Euromicro Conference on Digital Systems Design (DSD 2010), September 2010, France, pp. 459-466
- Jimit Shah, Komanduri S. Raghunandan and Kuruvilla Varghese “Area Optimized H.264 Intra Prediction Architecture for 1080p HD Resolution”, 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2010), July 2010, France, pp: 120-125
- Vikas.G, Joy Kuri, and Kuruvilla Varghese, “Power Optimal Network-on-Chip Interconnect Design”, 22nd IEEE International SOC Conference, September, 2009, Northern Ireland, UK, pp. 147-150
- Divyasree J, Rajashekar H, and Kuruvilla Varghese, “Dynamically Reconfigurable Regular Expression Matching Architecture” 20th IEEE International Conference on Application-specific Systems, Architectures and Processors 2008 (ASAP 2008), July 2008, Leuven, Belgium, pp. 120-125
- Gajanan Jedhe, Arun Ramamoorthy and Kuruvilla Varghese, “A Scalable High Throughput Firewall in FPGA”, The 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2008 (FCCM’08), April 2008, California, USA, pp. 43-52
Project: ASIC components for interfacing to various sensors in the next generation LCA
Sponsor: DeitY, Ministry of Communications and IT
The objective is to develop a prototype ASIC with the functionality of interfacing with one or more sensors in the next generation LCA aircraft. The current generation LCA aircraft’s electronics sub-systems for flight control are made out of imported Integrated Circuits. For example, the Air Data Computer is one of the key electronics subsystems in the light combat aircraft and interfaces to a number of sensors within the aircraft and digitizes and processes the signals from them and communicates with other air data computers in the aircraft. It is currently implemented using many discrete components on a printed circuit board (PCB). In this project, we would like to take the first steps towards this aim by identifying key components from the sub-system and design a custom chip to incorporate their functionality and show a proof of concept sub-system.
Superscalar 32-bit RISC-V CPU
Run-Time Reconfigurable Coprocessor for Training and Classification of Binary Weighted CNN
High Throughput Kernel Co-processor for Support Vector Machine