Prof. Mayank Shrivastava
Professor
Department of Electronic Systems Engineering
Indian Institute of Science Bangalore, 560012
Co-Founder, AGNIT Semiconductors Pvt. Ltd.
Investigator, Gallium Nitride EcoSystem Enabling Center (GaN Fab)
E-mail: mayank@iisc.ac.in
Web: http://mayank.dese.iisc.ac.in/
Contact: +91-80-2293-2732 / +91 9686340309

Biography

Prof. Mayank Shrivastava is a Full Professor at the Indian Institute of Science, Bangalore, and co-founder of AGNIT Semiconductors Pvt. Ltd., which is a deep-tech start-up in the semiconductor space. He is also instrumental in setting up Gallium Nitride prototyping Fab worth 300 Crores. He is also the past chair of the Micro & Nanoelectronics program of IISc Bangalore, which in his tenure became one of the most sought-after master’s programs in the country. Besides, he consults various semiconductor firms in the USA, Germany, and India.

He received his Ph.D. degree from the Indian Institute of Technology Bombay. For his Ph.D. work, he received Excellence in Research award and the Industrial Impact award from IIT Bombay in the year 2010.

He joined the Indian Institute of Science as a faculty member in the year 2013. Prior to joining IISc, he held positions in Infineon Technologies, Munich, Germany; Infineon Technologies, East Fishkill, USA; IBM Microelectronics, Burlington, USA; Intel Mobile Communications, Hopewell Junction, USA; Intel Corp, Mobile and Communications Group, Munich, Germany, between 2009 and 2013. His Ph.D. work and research contributions during the industry tenure have resulted in several key semiconductor devices, which capture a reasonable real state in advanced SoC and automotive chip products in the market today.   

Prof Shrivastava’s work has resulted in over 250 peer-reviewed international publications of high repute (around 55 of these papers are in IRPS and IEDM, the two most prestigious conferences of IEEE EDS where most of the breakthroughs are reported, and around 100 are in journals such as IEEE Transactions) and 57 patents. Most of these patents are either licensed by semiconductor companies or are in use in their products. He has guided/trained over 40 PhD students, over a dozen postdoc fellows, and over 100 master’s students and research staff.

He is among the first recipients of the Indian section of the American TR35 award (2010) and the first Indian to receive IEEE EDS Early Career Award (2015). He is also an Editor of IEEE Transactions on Electron Devices. Besides, he is an IEEE Electron Device’s Society (EDS) Distinguished Lecturer and an elected member of the IEEE EDS Board of Governors. He has also served on the technical and executive committees of over a dozen international conferences around the world.

Overall, he is a recipient of over 25 national and international awards, recognitions, and honors of high repute, such as the prestigious DST Swarnjayanti Fellowship (2021), Abdul Kalam Technology Innovation National Fellowship from INAE-SERB (2021), and the VASVIK award (2021), the National Academy of Sciences, India, (NASI) Young Scientist Platinum Jubilee Award – 2018; Indian National Academy of Science (INSA) Young Scientist Award – 2018; Indian National Academy of Engineering (INAE) Innovator Entrepreneur Award 2018 (Special commendation); Indian National Academy of Engineering (INAE) Young Engineer Award – 2017; INAE Young Associate (since 2017); Indian Academy of Sciences (IASc), Young Associate, 2018 – 2023; Ministry of Electronics & Information Technology (MeitY), Young Faculty Fellowship. Besides, he received best paper awards from several international conferences like Intel Corporation Asia academic forum, VLSI design Conference and EOSESD Symposium.

Prof Shrivastava broadly works on applications of emerging semiconductor materials like Gallium Nitride (GaN), atomically thin two-dimensional materials like Graphene and TMDCs, in electronic and electro-optic devices working closer to its fundamental limits (like the ability to handle extreme powers, ability to work at THz like ultra-high frequencies, or ability to compute information in unconventional ways). Besides, his group also works closely with semiconductor industries on developing novel device concepts for advanced CMOS and automotive nodes.

Prof. Shrivastava has also contributed to shaping India’s Semiconductor objectives via the white paper written for policymakers (as an outcome of the Electronics and Semiconductor vertical of VAIBHAV Summit, which he was leading), roadmap, and technology-specific inputs given to the ministry from time to time, critical inputs to the govt. and helping to establish connections with the semiconductor industry. Other than Semiconductors, he also writes and speaks on topics such as primary and higher education, the coaching system in India, brain drain, why Ph.D., industry affairs in India, entrepreneurship, etc. besides encouraging/motivating tens of thousands of young minds every year.

Work Experience

  1. Professor, Department of Electronic Systems Engineering, Indian Institute of Science Bangalore (June 2024 – Present).
  2. Associate Professor, Department of Electronic Systems Engineering, Indian Institute of Science Bangalore (June 2019 – June 2024).
  3. Assistant Professor, Department of Electronic Systems Engineering, Indian Institute of Science Bangalore (September 2013 – May 2019).
  4. Staff Engineer: Intel Corp. (MCG), Munich, Germany (April. 2013 – August 2013).
  5. Senior Engineer: Intel Corp. (MCG), Munich, Germany (Sep. 2011 – March 2013).
  6. Senior Engineer: Infineon Technologies, USA (Sep 2010 to Jan 2011) and Intel Corp. (MCG), USA, (Feb 2011 to Sep 2011).
  7. Visiting Scholar: Infineon Technologies, Munich, Germany. April 2008 to Oct 2008 & May 2010 to July 2010.

Entrepreneurial Experience  

  1. Co-Founder, AGNIT Semiconductors Pvt. Ltd.
  2. Investigator, Gallium Nitride Ecosystem Enabling Centre and Incubator (GEECI)

Contributions in Leadership Roles

  1. VAIBAHV Summit: This was the Indian Prime Minister’s effort to bring the Indian Diaspora under one roof. Prof. Shrivastava led the electronics/semiconductor vertical and could get the majority of the Indian diaspora under one roof to discuss/brainstorm various topics of collaborative interest. The proceedings ran for 3 weeks, which resulted in a 300-page report and a key policy document submitted to the Prime Minister’s office. This policy document has also helped shape the Indian Semiconductor Strategies and several new programs under the VAIBHAV initiative.   
  2. Gallium Nitride Fab: Prof. Shrivastava is instrumental in setting up Gallium Nitride Fab in India. This prototyping Fab would not only develop commercial equivalent GaN devices but would also support start-ups in the GaN technology arena.
  3. National Initiative on 2D Material-Based Future Technology Center: Prof. Shrivastava is driving this national effort: https://www.psa.gov.in/article/india-embarks-2d-materials-based-future-technologies/3595, which involved collaborating/interacting with several faculty members in IISc, over two dozen faculty members abroad, around 100 researchers from various leading institutions in India, around 15 industries and over 40 scientists from 11 strategic/govt. labs/policy offices while navigating towards an agreed-by-all roadmap for the proposed 2D center.
  4. IISc Master’s Program in Microelectronics & VLSI Design: Prof. Shrivastava was instrumental in transitioning it into the most sought-after master’s program in India for Electrical Engineering graduates and GATE toppers with a vibrant participation of Industry.        
  5. Popularizing Research Done in India: Prof. Shrivastava has been actively popularizing research work done in India and the potential that exists in India at many forums including Industries and academia around the world. His talk and writing on “Why Ph.D. – Breaking the Myths and Misconceptions” and his writings/talks on “Brain Drain” are quite well-received.
  6. IEEE Electron Device Society – Bangalore Chapter Chair: In his leadership, it not only became one of the most active EDS chapters but also attained a very high level of financial stability and independence.   
  7. International Conference on Emerging Electronics (ICEE): Prof. Shrivastava has been serving in the IEEE ICEE’s leadership/executive committee since 2018. In 2022 he served as the general chair. In this role, he led a team of over 170 experts (Industry and Academia) from around the world. His team transformed ICEE into one of the largest IEEE Electron Devices conferences in the world with participation from around the world having a significant fraction from leading semiconductor industries. The conference also resulted in over 300 outstanding scientific contributions, many policy suggestions, and a roadmap for the world to progress further in semiconductor technologies.   
  8. India ESD Forum: Until the Year 2023 there was barely any ESD knowledge/awareness in India. ESD is a key field related to semiconductor reliability. He started what is now called the India ESD Forum. This enabled connecting semiconductor industry professionals and systematically grew the community and knowledgebase from less than 5 (ten years back) to over 300 engineers in the industry today.
  9. Research Facility: He has built a one of its kind semiconductor and quantum device characterization and modelling facility in IISc. 
  10. National and International Advisory Committees: Prof. Shrivastava has also served in several national and international technical advisory committees, review committees, etc.

Key Industry Interactions

  1. Intel (Germany): To explore novel ESD device designs/architectures in FinFET nodes. This project resulted in 5 US patents (in use by Intel) disclosing several novel ESD device concepts in FinFET nodes. Besides, it resulted in several high-quality publications, one best paper award, and two PhD students.
  2. Intel (India): To explore the heat-spreading ability of graphene and the role of defects/grain boundaries in thermal transport across graphene. Subsequently, use the physical insights to develop efficient heat-spreading solutions using graphene and other 2D materials. This engagement is supporting one PhD student.
  3. Texas Instruments (USA): In the first phase (Year 2017-20) of the project the engagement was to explore the physics behind current filamentation and power scalability issues in LDMOS-SCR devices for advanced automotive nodes. In the second phase (The year 2020-23), we explored power-to-fail scalability issues in several device architectures in automotive nodes under IEC-like stress conditions. This project resulted in ESD robust LDMOS-SCR devices and several IEC robust ESD protection devices that are in use in TI’s products. Some of the TI products that were earlier plagued by early failure under system-level stress conditions have passed reliability qualification after adopting the design modifications proposed in this project. Besides, it resulted in several high-quality publications and two PhD students. Both the students were acquired later by TI. Phase three (The year 2023-26) has continued on the same thread while also modeling the complex failure dynamics under system ESD stress conditions. This engagement so far has supported four PhD students.
  4. Alpha & Omega Semiconductors (USA): This engagement was with the TVS group. We were chartered to explore/develop a range of TVS protection devices (4 unique products), which must be better than the devices available in the market while meeting a target datasheet. This project also graduated four postdocs, one hired by Nexperia (a leading semiconductor company in the UK) to lead the TVS group in the UK, and two others moved to AOS to lead the TVS development within AOS.
  5. Samsung (Korea): The project is to explore and invent novel ways to protect ESD phenomena in their advanced CMOS node, particularly for ultra-fast IO applications, where the need is to significantly suppress the parasitic capacitance and boost failure current per unit area. Besides, we are also building scalable models for SCR-based ESD protection devices.
  6. Samsung (India): Funded to build a Quantum Technology Lab.
  7. Keysight (India): Funded to build a Quantum Technology Lab.
  8. A Leading Semiconductor Company (Name Can’t be Disclosed): Technical Advisory Board of the company.
  9. Synopsys (India & USA): Funded resources worth USD 75M to start a new program titled: India Semiconductor Workforce Development Program.
  10. Semiconductor Complex Limited (SCL, India): Their base process was licensed from another company, which was limited to 1.8V core devices. To develop any SoC product one would need high voltage (LDMOS) devices of 10V, 14V, 40V, and 80V classes, and ESD protection devices. We developed the entire range of LDMOS devices for SCL, ported the processes, and qualified it for it to eventually appear in an extended PDK. More details are disclosed here: https://auto.economictimes.indiatimes.com/news/auto-components/iisc-technology-can-address-automotive-chip-shortage/89987058

Funding and Sponsors

So. No. Project Title Agency Value in Rs. (Lacs) Duration PI/Co-PI/Investigator
1 Institute Seed Grant for the Establishment of Advance Nanoelectronics Device & Circuit Research Laboratory IISc 34 Oct 2013 – Sep 2014 PI
2 Demonstration of Graphene based RF Transistors DRDO (SSPL) 10 June 2014 – Oct. 2014 PI
3 Exploration of Carrier Transport and Contact Resistance Behaviours in Carbon Nanotube and Graphene Devices Using Nanosecond Time Scale Charge Bust DST (SERB) 51 July 2014 – June 2017 PI
4 Investigation on GaN devices for power electronic switching applications and design and development of a high frequency GaN convertors topology NaMPET Phase-II 191 Oct. 2014 – March 2017 Co-PI
5 Advance Nanoscale Characterization Facility IISc 110 Jan 2015 – Sep 2015 PI
6 ESD Reliability of sub-14nm node technologies Intel, Germany 150K USD Dec 2015 – Nov. 2018 PI
7 12th Plan Grant to Develop Laboratory Space IISc 5 Sep 2016 – March 2017 PI
8 Technology Development for 600V Normally – OFF Gallium Nitride Transistor for Reliable Power Electronic Systems DST (TSDP) 1028 May 2016 – August 2020 PI
9 Graphene Based THz Transistor Technology DRDO (ERIPR) 500 March 2017 – March 2023 PI
10 High Voltage & ESD Device Development & Enablement in SCL’s 180nm CMOS Technology IMPRINT 300 March 2017 – March 2021 PI
11 Detailed Project Report on GaN Foundry DeitY 60 March 2016 – Sep. 2016 Co-PI
12 Power-scalability of Advance Semiconductor Devices from ESD time domain to DC Texas Instruments (USA) 165K USD Oct 2017 – Sep 2020 PI
13 2D Material Based Transistor Technology NNeTRA program of MeitY
(Under CEN-III)		 150 (sub-project) April 2018 – March 2022 Co-PI
(PI of sub-project)
14. Exploratory Project under IOE IISc/MHRD 200 August 2019 – March 2020 PI
15. Advance Nanoscale Characterization Facility (II) IISc (MHRD) 150 March 2018 – Sep. 2018 PI
16. Graphene Based Heat Spreader Technology IMPRINT-II 140 – PI
17. HV ESD Protections Design for On-Chip IEC ESD TI, USA 210K USD Oct. 2020 – Sep. 2023 PI
18. Development of New TVS Product and Technology AOS, USA 450K USD Nov. 2020 – Oct. 2023 PI
19. Performance and Reliability Co-Design of e-mode GaN HEMTs DST, SERB (CRG) 66 September 2021 – August. 2024 PI
20. A Novel Memory Synapse Technology for Neuromorphic Computing DST, SERB 380 March 2022 – Feb 2027 PI
21. Development of On-board (In-Vehicle) Fast DC Chargers Using High-Speed GaN HEMTs for Two-Wheeler (2W) Electric Vehicles MeitY 450 April 2022 – March 2024 PI
22. Development of Rugged 30A/650V e-mode Power HEMT Technology and Fast 1kW DC Charger using the in-house Developed Power HEMT DST, AMT 1038 April 2022 – March 2025 PI
23. GaN-Based THz Devices (Abdul Kalam Fellowship) INAE 75 Oct. 2021 – Sep. 2026 PI
24. Industry Grants For Microelectronics Lab Several Industries 75 2019 – 2022 PI
25. High-Speed ESD Protection Design in Advanced CMOS Nodes Samsung 360 Sep. 2022 – Sep. 2025 PI
26. Performance-reliability Co-design Approach for High-performance and High Reliability Normally OFF Vertical β-Ga2O3 Field Effect Transistors (FETs) DST SERB 60 Jan 2023 – Dec 2025 PI
27. Graphene-Based Heat Spreader with Thermal Conductivity Crossing 3000 W/m-K for Next Generation Electronic Systems Intel 80 Oct. 2023 – Sep. 2025 PI
28. Capital Support to Develop Quantum Technology Lab Samsung 300 Sep. 2023 – March 2024 PI
29. Capital Support to Develop Quantum Technology Lab Keysight 40 Jan. 2023 – March 2023 PI
30. Explorative Investigations Related to IEC Stress in Automotive Technologies Texas Instruments, USA 420K USD Jan 2024 – Dec. 2027 PI
Total Sanctioned Funding till Sep. 2023

7320

Lakhs

 ~9M USD*

*This doesn’t include the $50M funding received for setting up a prototyping GaN Foundry and $75M worth of computational resources received from Synopsys.

Facility

Research Facility in MSDLab

This is a ~40 Crore worth facility. The unique capabilities of this facility are being extensively utilized, not just by PhD students in MSDLab, but also by staff and students from several other departments. In general, this facility has helped develop several technologies such as graphene and 2D materials technology, high power Gallium Nitride technology, organic electronics and Si based power technology. The users can independently handle the tool post a systematic training.

1. Manual Probe Station

Lab has 3 manual probe stations. The tool allows holding and probing samples of 1cm size to 8-inch wafers. The probe station houses a high-end microscope with magnification up-to 1000, which allows probing nano-meter sized devices for DC and RF tests at temperatures between 300K to 500K. Besides, its capable of measuring ultra-low currents, as well as very high currents and voltages. The vibration free table with pneumatic isolation using a low noise air compressor allows high precision probing of the devices.

2. Semi-automatic Probe Station

It enables automatic DC and RF device characterization (up to 110 GHz), wafer-level reliability, e-test, modelling, or yield analysis. It is equipped with probe station control software to automate the measure 1000s of devices with a single click.

3. Range of Wafer Level Electrical Characterization Equipment

The facility has the following electrical characterization tools.

Equipment Type

Make

Model

Specification

SMU (4 Nos)

Keithley 2400

Keithley 2400

General purpose SMU (100V, 1A)

SMU (2 Nos)

Dual Channel SMU

Keithley 2635B

Single Channel SMU capable of 1A DC (10A Pulse), 200V.

SMU

Dual Channel SMU

Keithley 2636B

Dual Channel SMU capable of 1A DC (10A Pulse), 200V

SMU

Dual Channel SMU

Keysight

Dual Channel SMU capable of 1A DC, 200V

HC SMU (2 Nos)

High Current SMU

Keithley 2651A

High Current SMU (Upto 50A in pulsed mode, 20A in DC mode)

HV SMU (7 Nos)

High Voltage SMU

Keithley 2657A

High Voltage SMU (Upto 3kV)

CV Meter

CVU

Keithley PCT-CVU

High voltage capacitance measurements

Switching Matrix

Switching Matrix

Keithley 707B

Six-slot semiconductor switch mainframe (8 input and 36 output ports)

High Power interface panel

Panel

Keithley 8020

Interface between the Parametric Curve Tracer (PCT), SMUs, probe station and test fixtures for wafer level high power measurements.

Parametric Curve Tracer (2 Nos)

4200

4200A-SCS

Parametric curve tracer with automation capability and switching matric for semiconductor device characterization. It consists of 6 medium power SMU, 1 CVU and 2 pulse measurement units.

FFT Spectrum Analyzer

SR760

SR760

Single-channel 100 kHz FFT spectrum analyzer

Digital Phosphor Oscilloscope

DPO

DPO 70404C

4 GHz digital oscilloscope

High speed pulse generator

HSPG

AVR-E3-B-W3

100 V, 1 ns to 5000 ns pulse generator

Arbitrary Function Generator (3 Nos)

AFG

AFG1022

µHz to MHz, mV to 10 V, dual channel function generator

4 Channel Digital Storage Oscilloscope (2 Nos)

DSO

TBS1154

150 MHz, 4 channel oscilloscope

Lock-in Amplifier

MFLI

MFLI

500 kHz Lock-In Amplifier
4. Transmission Line Pulsing

Transmission line pulse setup is used to generate electrical pulses at a very high frequency with high amplitudes. At these frequencies, wavelength of electrical signal reaches the length scales of the testing setup and a proper pulse shaping is difficult. Due to these issues, a conventional SMU cannot be used for this purpose and a specialized strategy is needed. The TLP pulse generator works on the principle of transmission line pulsing technique. The TLP generator can generate pulses in pulse width range of 1ns-1.5 us with a maximum voltage level of 2 kV.

5. Micro Raman, EL/PL Setup with UV and Visible Lasers

Raman spectroscopy works on the principle of inelastic scattering of light by a material. As the light is applied on a material, the following interactions take place: Rayleigh scattering, Stokes scattering and Anti-stokes scattering.  Raman setup works on the principle of stokes and anti-stokes scattering, and is used to study chemical and vibrational properties of a material. A laser source with a pre-determined wavelength and power density is used and a charge couple detector is used to capture photons emitted from the material upon interaction with light. The setup has the following two light sources: (1) DPSS, green-colour, 532 nm and (2) UV light, 325 nm. The setup also comprises of electrical part used to study material change with stress application. A cryogenic pump, with an ability of cool down as low as 4K, is integrated with the Raman setup to study device interactions at extremely low temperatures. This study is used to study ambient interactions, photoluminescence, electroluminescence, impact of electrical stress on chemical properties and low temperature vibrational properties of a material.

7. Custom Setup for 2D Material Based Stamping and Device Fabrication inside Glovebox

This custom developed tool provides an inert environment for fabrication of devices using materials sensitive to oxygen and moisture (less than 1ppm of Oxygen and moisture). This enables development of heterostructures using dry transfer setup called stamping stage having high magnification (2000x) microscope and range of nano-manipulators, provides an efficient way to explore fundamental properties and application specific behaviour of various potential materials for electronic applications. The setup also consists of thermal evaporator for metal deposition and wet-bench. Such an assembly of stamping stage and thermal evaporator inside inert atmosphere enables an ultra-clean process for device fabrication.

8. 3K Ultra Low Vibration Close-Loop Cryocooler for Optical and Electrical (DC & RF) Measurements

This tool allows loading devices under ultra-low temperature (3K) condition and enables optical as well as electrical excitations / measurements.

9. L-N2 Semi-automatic Probe Station

This is a L-N2 based semi-automatic probe station. The tool enables DC and RF device characterization, wafer-level reliability, e-test, modelling, or yield analysis for a temperature ranging from 77K to 550K. It is equipped with a probe station control software to automate measurements for 1000s of devices.

10. Deep Level Transient Spectroscopy

This tool allows probing deep level defect / trap states in materials.

11. Thermo Reflectance Spectroscopy

This tool allows probing temperature across a nanoscale device with sub-400nm special resolution and sub-ns time resolution.

12. Wafer Level Semiconductor Device Reliability Characterization Suit

This tool allows to study high field reliability behaviour of semiconductor devices such as HCI, TDDB, NBTI, PBTI and other similar issues in emerging devices.

13. High End Computational Cluster

With over 500 Cores and more than 6TB RAM, this is among the most powerful cluster being used for TCAD simulations and Atomistic computations.

14. Parametric Curve Tracer with sub-50ns pulse I-V measurement capability

The lab has two such systems from Keithley (Keithley 4200 SCS), which consists of 6 medium power SMUs (each), capacitance-voltage measurement unit and two sets of pulse measurement units (PMU). It allows measurement from fA to A. It can also measure pulse I-V characteristics with 50ns pulse width.

15. 1/f Noise Measurement Setup

This enables 1/f Noise measurements in range of devices.

16. 3-Omega setup for thermal conductivity measurements

 

17. Atomic Force Microscopy (AFM)

AFM with additional modes such as CAFM, KPFM, SThM, STM, SCM, SSRM, IV Spectroscopy, Lthography, Piezoelectric studies, etc which offers flexibility to perform surface studies and material response to electrical studies.

18. Pulse Raman, Wafer Scale Electroluminescence Mapping, Dark Field Microscopy

Setup for pulsed Raman is available for precise material studies. Electroluminescence mapping, dark field microscopy enhances the surface observation capabilities for identification and processing of novel crystals based devices.

19. 67 GHz PNA -X Network Analyzer

PNA -X Network Analyzer by Keysight (N5247) capable of going upto 67 GHz for Semiconductor Characterization.

20. Advanced TLP Setup

Transmission line pulse setup is used to generate electrical pulses at a very high frequency with high amplitudes. At these frequencies, wavelength of electrical signal reaches the length scales of the testing setup and a proper pulse shaping is difficult. Due to these issues, a conventional SMU cannot be used for this purpose and a specialized strategy is needed. The TLP pulse generator works on the principle of transmission line pulsing technique. The TLP generator can generate pulses in pulse width range of 1ns-1.5 us with a maximum voltage level of 2 kV. A better oscilloscope would help in better time domain resolution of the captured waveforms.

21. Wafer Level HBM Tester with Waveform Capture

Our lab specializes in automated commercial testing routines and this wafer level tool aims to test the response of HBM standard at wafer scale to statistically establish the reliability trends. With the waveform capture capability, response of failed devices can be thoroughly analyzed.

22. GaN and SiC transient reliability testing setup

GaN and SiC are some of the most popularly used materials for power applications. Commercial integration of novel power devices calls for thorough understanding of response of all on-chip components to various transients. This setup will help to test and establish the transient reliability of these devices.

23. Transient Interferometric Setup

TIM setup allows a user to map the hotspot movement in the device active area and the pathways thorough which a device would dissipate heat. This is much required while planning thermal layouting of devices.

24. CVD Reactor for Graphene

Graphene is the by-far the most popular 2D material and its electronics-level high quality growth is much needed to be explored.

25. CVD Reactor for TMDs

Chemical vapor deposition setup for large area monolayer TMD growth of high quality. Control on growth step allows for controllable doping and material-level properties.

26. Nanosecond high power pulse IV setup (From Focus Microwave)

Electrical overstressing is a very big reliability concern when planning and designing devices for commercial application grades. Ultrafast time scales and high power SMU setups allows to study degradation and response of devices to electrical overstressing in steps.

Arriving Soon…

Expansion of lab facilities is already underway with new tools and capabilities being added and setup. Extensive reliability exploration and close control on material growth is being achieved to spearhead the novel semiconductor research.

1. 4K cryo-probe station with RF measurement capability (upto 40 GHz)

This tool would allow to go down to ultra-low temperatures and provide a capability to perform RF measurements of devices.

2. Single photon detection setup
3. 10mK Dilution Fridge with 8T Magnet, 24 DC and 10 RF Lines
4. Qubit Control System for upto 2 Qubits

Research Group

PhD Students

  1. Raising Archana Bairiganjan Mohapatra (M-Tech: IIT Kharagpur)
  2. Atharv Shrivastava (GATE Rank: 189)
  3. Deshpande Ajinkya Charudatta (B-Tech: NIT Nagpur, GATE Rank: AIR 377)
  4. Mayookha S Lekshmi (B-Tech, NIT Calicut, GATE Rank: 2234)
  5. Megha Yadav (M-Tech: IIT Gandhinagar)
  6. Bachawar Vinod Kumar (GATE Rank : 924)
  7. Vettrivelan M (GATE Rank : 485)
  8. Mayank Yadav (GATE Rank: 955)
  9. Shravya N Raj (GATE Rank: 1500)
  10. Shreenidha K K (GATE Rank: 1336)
  11. Harihar Nath (M-Tech: NIT Delhi)
  12. Aadil Bashir Dar (NIT Srinagar, IIT Kanpur)
  13. Harsh Raj (B-Tech + M-Tech: IIT Kanpur, PMRF)
  14. Mitesh Goyal (B-Tech: NIT Trichy, Associate Director, Samsung)
  15. Subhajit Majumder (B-Tech: IIST Trivandrum, Senior Engineering Scientist, ISRO)
  16. Mehak Ashraf Mir (JMI, NIT Srinagar, PMRF)
  17. Asif Altaf Shah (M-Tech: NIT Srinagar, PMRF)
  18. Mohammad Ateeb Munshi (M-Tech: NIT Srinagar, PMRF)
  19. Rasik Rashid (M-Tech: NIT Srinagar, PMRF)
  20. Anand Rai (B-Tech: NIT Patna, PMRF, GATE Rank: 113)
  21. Utpreksh Patbhaje (B-Tech: IIIT Jabalpur, PMRF, GATE Rank: 925)
  22. Rupali Verma (B-Tech: NIT Patna, PMRF)
  23. Pavithra N (Primary Guide: Prof. Praveen Ramamoorthy)
  24. Rajarshi Roy Chaudhuri (M-Tech: IIEST Shibpur, Inspire Fellow, Current Joint PostDoc Fellow with Infineon Technologies and TU Vienna, Austria)
  25. Monish Murali (2023, B-Tech: PESIT, GATE Rank: 397, TI Fellow, Currently with Texas Instruments)
  26. Aakanksha Mishra (Joint PhD Students with IIT Delhi, Now with Infineon Technology, Munich, Germany)
  27. Vipin Joshi (Joint PhD Students with IIT Jodhpur, Now Assistant Professor in BITS Pilani, Goa Campus)
  28. Sayak Dutta Gupta (2022, M-Tech: IIEST Shibpur, Inspire Fellow, Joined Infineon Technologies, Germany, Currently Assistant Professor in IIT Madras)
  29. Jeevesh Kumar (2022, B-Tech: NIT Trichy, CSIR-UGC NET Rank: 71, CSIR Fellow, Currently Assistant Professor in IIT Dhanbad)
  30. Harsha B (2022, B-Tech: GEC Trissur, GATE Rank: 414, Currently with AOS)
  31. Hemanjaneyulu Kuruva (2021, M-Tech: IISc Bangalore, Visvesvaraya Fellow, Currently with Lam Research)
  32. Ansh (2021, B-Tech: NERIST Itanagar, UT Austin, Fulbright Fellow, IMEC, Belgium, Currently with Micron, USA)
  33. Kranthi N. K. (2021, M-Tech: NIT Calicut, Visvesvaraya Fellow, Currently with Texas Instruments)
  34. Ankit Soni (2021, B-Tech: NIT Hamirpur, GATE Rank: 864, Visvesvaraya Fellow, Now with Global Foundry)
  35. Rajat Sinha (2021, B-Tech: BIT Mesra, GATE Rank: ~500, Currently with Micron)
  36. Bhawani Shankar (2020, M-Tech: BITS Pilani, Stanford University, Currently with Power Integrations, USA)
  37. Adil Meersha (2020, B-Tech: NIT Calicut, GATE Rank: 21, University of Cambridge, Currently with Paragraf (A Graphene Company), UK)
  38. Abhishek Mishra (2020, M-Tech: IIITM Gwalior, University of Bristol, Currently with A-Star, Singapore)
  39. Milova Paul (2020, M-Tech: DTU Delhi, Currently with Intel, Portland, USA)
  40. Sampath B (2020, M-Tech: NIT Nagpur, Currently with Global Foundry, Singapore)

Postdoctoral Fellow

  1. Mahesh Vaidya (Ph.D. NIT Raipur, Samsung Fellow)
  2. Vipin Joshi (Ph.D. IITJ, Currently Assistant Professor in BITS Goa)
  3. Jeevesh Kumar (Ph.D. IISc, Currently Assistant Professor in IIT Dhanbad)
  4. Harsha B Variar (Ph.D. IISc, Currently with AOS)
  5. Suruchi Sharma (Ph.D. NIT Delhi, Currently with AOS)
  6. Satendra Kumar Gautam (Ph.D. IIT Roorkee, Currently with Nexperia, UK)
  7. Kalyan Jyoti Sarkar (Ph.D. IIT Kharagpur, DST SERB NPDF, Now with TU Dresden)
  8. Ashita Kumar (AOS Fellow)
  9. Nikhil K S (Ph.D. IITM, Assistant Professor, NIT Calicut)
  10. Asha Yadav (Ph.D. IITG, Currently with University of Calgary)
  11. Jhnanesh Somayaji (Ph.D. NIT Karnataka, Currently with Global Foundry)
  12. Ajay (Currently with Global Foundry)
  13. Vinila Bedekar (Ph.D. BARC, Currently with FutureBridge)

Trained and Guided over 100 Masters Students and Project Staff

Teaching

Course title (Click to see Syllabus)

1. Basics of Semiconductor Devices and Technology
 
2. Microelectronics Lab
 
3. Physics and Design of Transistors
 
4. Design of Power Semiconductor Devices
 
5. Reliability of Nanoscale Circuits and Systems
 
6. Design of Power Semiconductor Devices
 
7. Microelectronics Technology For VLSI Engineers
 
8. VLSI Design Principles for Device Engineers

Professional Recognitions, Awards, and Fellowships

  1. SwarnaJayanti Fellowship, DST, 2021 – 2026
  2. VASVIK Award, Year 2021
  3. IEEE Electron Devices Society Board of Governors (2023 – 2025)
  4. IEEE Electron Devices Society Distinguished Lecturer
  5. Editor, IEEE Transactions on Electron Devices (2022 – 2025)
  6. Abdul Kalam Technology Innovation National Fellowship, INAE, 2021 – 2026
  7. National Academy of Sciences, India, (NASI) Young Scientist Platinum Jubilee Award – 2018
  8. Indian National Academy of Science (INSA) Young Scientist Award, 2018
  9. Indian National Academy of Engineering (INAE) Innovator Entrepreneur Award 2018 (Special commendation)
  10. Indian National Academy of Engineering (INAE) Young Engineer Award, 2017
  11. IEEE EDS Early Career Award – 2015, one of the highest honors given by IEEE Electron Device Society (EDS).
  12. INAE Young Associate (since 2017)
  13. Indian Academy of Sciences (IASc), Young Associate, 2018 – 2023
  14. Department of Electronics & Information Technology (DeitY), Govt. of India, Young Faculty Fellowship for the duration of 2016 – 2020.
  15. Outstanding Paper Award, 38th EOSESD Symposium, 2017
  16. Best Paper Award, 30th IEEE VLSI Design Conference, Jan. 2017
  17. Best Paper Award, 6th IEEE ICEE, Dec 2022
  18. Editor for Elsevier Microelectronic Reliability (2018 – 2020)
  19. TR35, 2010, Young Innovator Award. Technology Review’s TR35 list by Massachusetts Institute of Technology recognizes the outstanding innovators under the age of 35 each year. Received on March 8, 2010
  20. Award for Excellence in Thesis Work, IIT Bombay-2010, received on 6th August, at the 48th convocation of IIT Bombay.
  21. IIT Bombay – Industrial Impact Award, for pursuing research work that caused maximum industry impact. Received on September 6, 2010 by Dr. N. Mukunda, who is a prominent Indian scientist.
  22. Best Research paper Award, Intel Asia Academic Forum 2008, Oct 2008, Taipei, Taiwan
  23. Infineon Fellowship, Duration: November 2008- July 2010
  24. IEEE Electron Device Society Committees
    1. Technical Committee for Wideband gap Semiconductors
    2. Technical Committee for Reliability Physics
    3. Membership Committee
  25. Conference Leadership & Technical Program Committee (TPC) IEDM and IRPS are the two most prestigious conferences
    1. General Co-Chair, IEEE EDTM, 2024
    2. Sponsorship Co-Chair, IEEE EDTM, 2023
    3. Organizer, 14th RPGR (Recent Progress in Graphene Research), 2023
    4. General Chair, IEEE ICEE, 2022
    5. Sub-committee Chair, EOSESD Symposium, USA, 2021
    6. Technical Program Committee, IEEE EDTM, 2019
    7. General co-Chair, IEEE ICEE, 2020
    8. Technical Program Committee Chair, IEEE ICEE, 2018
    9. General co-Chair and Technical Program Committee Chair, IEEE CONECCT, 2018
    10. Technical Program Committee, IEEE International Electron Device Meeting (IEDM), 2019
    11. Technical Program Committee, IEEE International Electron Device Meeting (IEDM), 2018
    12. Vice-chair, “Device and Process Technology” Track, IEEE VLSI Design Conference, 2014 & 2015
    13. IEEE International Reliability Physics Symposium (IRPS), USA, 2017 – 2021
    14. Sub-committee Chair, EOSESD Symposium, 2017
    15. IEEE ESREF, Europe, 2019
    16. IEEE ESSDERC, Europe, 2014 – 2016
    17. Sub-committee Chair, EOSESD Symposium, 2014
    18. Technical Program Committee, EOSESD Symposium, 2012 – 2021
    19. General Chair, India ESD Workshop, 2015 – 2020

Science Outreach Through Electronic and Print Media

With IISc Affiliation:

Deccan Herald: https://www.deccanherald.com/india/karnataka/bengaluru/iisc-synopsys-tie-up-to-train-next-gen-semiconductor-workforce-2740179
NDTV: https://www.ndtv.com/education/iisc-software-company-synopsys-collaborate-to-bridge-indias-semiconductor-workforce-gap-4506616
Notopedia: https://www.notopedia.com/board-details/28607/1/IISc-And-Synopsys-Partner-To-Close-Semiconductor-Workforce-Gap-In-India
Techmag: https://www.technologymagazine.org/iisc-partners-with-synopsys-to-train-next-generation-semiconductor-workforce/
IISc Bulletin: https://iisc.ac.in/events/iisc-and-synopsys-collaborate-to-address-the-global-semiconductor-workforce-shortage/
BusinessLine: https://www.thehindubusinessline.com/companies/samsung-iisc-sign-mou-to-set-up-quantum-technology-lab/article67438414.ece
The Economic Times: https://economictimes.indiatimes.com/tech/technology/samsung-semiconductor-india-research-iisc-in-pact-for-research-on-quantum-technologies/articleshow/104554472.cms
The Indian Express: https://indianexpress.com/article/cities/bangalore/samsung-semiconductor-india-research-iisc-quantum-technology-lab-8991203/
Times Now: https://www.timesnownews.com/education/iisc-samsung-semiconductor-india-research-collaborate-to-set-up-a-quantum-technology-lab-article-104570527
EE Times: https://www.eetindia.co.in/samsung-semiconductor-and-iisc-collaborate-on-quantum-research/
Analytics India Magazine: https://analyticsindiamag.com/samsung-and-iisc-partner-to-set-up-a-quantum-technology-lab/
Business World: https://www.businessworld.in/article/Samsung-IISc-Join-Forces-To-Establish-Quantum-Technology-Lab/19-10-2023-495624/
Digital Learning: https://digitallearning.eletsonline.com/2023/10/iisc-and-ssir-ink-mou-to-establish-quantum-technology-lab/
Pune News: https://pune.news/science/quantum-technology-research-gets-a-boost-as-samsung-joins-forces-with-iisc-70666/
IISc Bulletin: https://iisc.ac.in/events/samsung-semiconductor-india-research-and-indian-institute-of-science-collaborate-to-drive-research-on-quantum-technologies/
Financial Express: https://www.financialexpress.com/education-2/ssir-and-indian-institute-of-science-join-hands-to-boost-semiconductor-rampd-in-india/2975087/  
Economic Times: https://economictimes.indiatimes.com/tech/technology/samsung-semiconductor-india-research-iisc-join-hands-to-boost-india-semiconductor-rd/articleshow/97726429.cms  
ToI: https://timesofindia.indiatimes.com/business/india-business/samsung-semiconductor-india-research-and-indian-institute-of-science-partner-to-boost-semiconductor-rd/articleshow/97728143.cms  
Analytics India: https://analyticsindiamag.com/samsung-partners-with-iisc-to-drive-semiconductor-innovation/  
The Hindu: https://www.thehindubusinessline.com/business-tech/samsung-semiconductor-india-research-iisc-partner-to-boost-rd-in-semiconductor/article66484614.ece/amp/  
Deccan Herald: https://www.deccanherald.com/amp/business/technology/iisc-samsung-wing-join-hands-for-semiconductor-rd-project-1189126.html  
Outlook India: https://www.outlookindia.com/business/iisc-to-collaborate-with-samsung-in-advanced-nanoelectronics-device-research-news-260490  
PTI News: https://www.ptinews.com/news/business/iisc-to-collaborate-with-samsung-in-advanced-nanoelectronics-device-research/4/510189.html  
Economic Times: https://auto.economictimes.indiatimes.com/news/auto-components/iisc-technology-can-address-automotive-chip-shortage/89987058
News 18: https://www.news18.com/news/auto/researchers-at-iisc-collaborating-to-provide-solution-for-chip-shortage-in-auto-industry-4837550.html
Indian Express: https://indianexpress.com/article/cities/bangalore/iisc-bengaluru-research-chip-shortage-7800829/
Bhaskar: https://www.bhaskarlive.in/iisc-technology-can-address-automotive-chip-shortage/
My News 24×7: https://mynews24x7.in/iisc-technology-can-address-automotive-chip-shortage-et-auto/
News Network: https://todaynewsnetwork.in/indian-institute-of-science-technology-could-help-address-automotive-chip-shortage/
Times Bureau: https://thetimesbureau.com/to-solve-chip-shortages-iisc-researchers-have-developed-a-resilient-high-voltage-automotive-technology-platform-202203/
Business Bytes: https://www.buzinessbytes.com/technology/iisc-technology-can-address-automotive-chip-shortage/
Lokmat Times: https://www.lokmattimes.com/technology/iisc-technology-can-address-automotive-chip-shortage/
Gadgets Now: https://www.gadgetsnow.com/tech-news/iisc-technology-can-address-automotive-chip-shortage/amp_articleshow/89991291.cms
Ahmedabad Mirror: https://ahmedabadmirror.com/iisc-technology-can-address-automotive-chip-shortage/81823583.html
India Today: https://www.indiatoday.in/education-today/news/story/iisc-bangalore-s-swarnajayanti-awardee-is-researching-on-materials-to-make-computers-more-efficient-1907180-2022-02-01
DST: https://dst.gov.in/swarnajayanti-awardee-bangalore-working-materials-can-make-computers-more-efficient
Telegraph: https://www.telegraphindia.com/edugraph/news/iisc-bangalore-professor-researches-on-mimicking-functions-that-the-brain-can-perform-rapidly/cid/1850185
Business Insider: https://www.businessinsider.in/science/research/news/iisc-scientist-develops-material-that-can-help-computers-mimic-brain-like-functions/articleshow/89263106.cms
Deccan Herald: https://www.deccanherald.com/science-and-environment/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function-1076764.html
Kalinga TV: https://kalingatv.com/technology/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function/
Gadgets Now: https://www.gadgetsnow.com/tech-news/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function/amp_articleshow/89264611.cms
National Herald: https://www.nationalheraldindia.com/amp/story/science-and-tech/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function
Ahmedabad Mirror: https://ahmedabadmirror.com/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function/81819733.html
Social News: https://www.socialnews.xyz/2022/01/31/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function/
Tripura India: https://www.tripuraindia.in/update/index/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function
Block One Daily: https://blockonedaily.com/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function/
Mangalore Mirror: https://www.mangaloremirror.com/swarnajayanti-awardee-from-bangalore-working-on-materials-that-can-make-computers-more-efficient/
Indian Express: https://indianexpress.com/article/cities/bangalore/bengaluru-scientists-swarnajayanti-fellowships-7613187/
IISc Press: https://iisc.ac.in/events/35034/
Aljazeera: https://www.aljazeera.co.in/business/three-bengaluru-scientists-awarded-swarnajayanti-fellowships/
New Indian Express: https://www.newindianexpress.com/cities/bengaluru/2021/nov/09/three-bengaluru-scientists-get-swarnajayanti-fellowships-2381168.html
Republic World: https://m.republicworld.com/india-news/education/17-scientists-awarded-swarnajayanti-fellowships-for-innovative-research-ideas.html
Business Bytes: https://www.buzinessbytes.com/news/national-news/swarnajayanti-fellowship-awarded-to-scientists-from-bangalore/
Ministry of Science & Technology (English Release): https://pib.gov.in/PressReleasePage.aspx?PRID=1705691
Ministry of Science & Technology (Hindi Release): https://pib.gov.in/PressReleasePage.aspx?PRID=1705750
DST: https://dst.gov.in/new-technology-high-electron-mobility-transistor-will-make-india-self-reliant-power-transistor
Bangalore Mirror: https://bangaloremirror.indiatimes.com/bangalore/cover-story/e-ncredible-india/articleshow/81575854.cms
Kashmir News: https://kashmirnewsbureau.com/scientists-from-bangalore-develop-highly-reliable-hemt/
Swarajya Magazine: https://swarajyamag.com/insta/indian-scientists-develop-indigenous-normally-off-high-electron-mobility-transistor-for-power-electronics
News20: https://news20-20.com/new-technology-for-hemt-developed/
Adda247: https://www.adda247.com/upsc-exam/daily-gist-of-the-hindu-pib-indian-express-and-other-newspapers-18-march-2021/
Rajya Sabha TV: https://www.youtube.com/watch?v=ASJ2H-NV7hw
Research Matters: https://researchmatters.in/news/iisc-develops-india%E2%80%99s-first-e-mode-gallium-nitride-power-transistor
Times of India: https://timesofindia.indiatimes.com/home/science/iisc-faculty-change-game-with-indias-first-e-mode-gallium-nitrade-power-transistor/articleshow/69661844.cms
Electronic for You: https://academia.electronicsforu.com/iisc-researchers-develop-indias-first-e-mode-gallium-nitride-power-transistor
Northbound: http://www.northbound.co.in/engineering-phd/
Research Matters: https://researchmatters.in/news/iisc-research-pushes-reliability-and-operating-limits-ultra-dense-finfet-system-chips
EE Herald: http://www.eeherald.com/section/news/owns20171225001-india-ee-edu.html
Research Matters: https://researchmatters.in/article/inae-announces-young-engineer-awards-2017
India DST: https://indiadst.wordpress.com/2017/01/20/iisc-researchers-develop-new-graphene-based-transistor-technology/
Scientifist: http://scientifist.com/iisc-researchers-graphene-electronics/
Indian Express: http://indianexpress.com/article/technology/science/breaking-the-graphene-barrier-4465396/
Bangalore Mirror: http://bangaloremirror.indiatimes.com/bangalore/others/iisc-can-make-your-wifi-1000-times-faster/articleshow/56091767.cms
IISc Press: https://researchmatters.in/article/iisc-scientists-new-discovery-yields-giant-leap-graphene-transistor-performance
The Better India: http://www.thebetterindia.com/79060/iisc-working-making-wifi-1000-times-faster/
UC News: http://www.ucnews.in/news/702-513932134192309/a-team-of-researchers-from-iisc-bangalore-could-make-our-wifi-1000-times-faster.html
Yahoo: https://in.news.yahoo.com/team-researchers-iisc-bangalore-could-095934372.html
Indian 364: http://www.indian364.com/technology/26961/Breaking-the-graphene-barrier
Research Matters: https://researchmatters.in/article/iisc-scientists-new-discovery-yields-giant-leap-graphene-transistor-performance
Rajya Sabha TV: https://youtu.be/k9u2Ji9Vlbk
Bangalore Mirror: http://www.bangaloremirror.com/bangalore/others/New-transistor-design-is-a-breakthrough/articleshow/49897633.cms
Indian Express: http://indianexpress.com/article/technology/technology-others/from-the-lab-a-new-device-for-more-efficient-phones-computers/
IISc Press: http://iisc.researchmedia.center/article/iisc-researcher%E2%80%99s-new-transistor-design-%E2%80%93-breakthrough-chip-technology
Indian Express: http://www.newindianexpress.com/cities/bengaluru/IISc-Prof-Wins-Major-Global-Award/2015/10/29/article3102225.ece
Deccan Herald: http://www.deccanherald.com/content/515146/bengaluru-scientist-wins-coveted-ieee.html
Hindu: http://www.thehindu.com/news/cities/bangalore/honour-for-iisc-professor/article7816056.ece
Global Indians: http://www.globalindian.indiaincorporated.com/iisc-prof-wins-major-global-award/
IEEE: http://eds.ieee.org/early-career-award.html
IISc Press:: http://iisc.researchmedia.center/article/iisc-professor-wins-major-international-award
Deccan Herald: http://www.deccanherald.com/content/509822/iisc-faculty-devises-technology-shrink.html
News Central: http://newscentral.exsees.com/item/8563b69c9b5b9519487c36e18dcedb90-f39db1effc9ea34e1d52a76b94b3ea02
Gas & Electricity: http://gaselectricity.in/iisc-faculty-devises-technology-to-shrink-power-electronic-systems
Daily Hunt: http://m.dailyhunt.in/news/india/english/deccan-herald-epaper-deccan/iisc-faculty-devises-technology-to-shrink-power-electronic-systems-newsid-45850179
Nyooz: https://www.nyoooz.com/news/bengaluru/245362/iisc-prof-wins-major-global-award/
GK Today: https://www.gktoday.in/quiz-questions/who-became-the-first-indian-to-bag-ieee-electron-devices-society-early-career-award/

Before joining IISc:

Technology Review: http://www2.technologyreview.com/tr35/profile.aspx?TRID=860
DNA: http://www.dnaindia.com/india/report-iit-b-makes-it-to-mit-s-top-innovators-list-1361475
Deccan Herald: http://www.deccanherald.com/content/58465/beyond-classroom.html
Indian Express: http://www.indianexpress.com/news/towards-smaller-better-gadgets/587650/0
NDTV: http://www.ndtv.com/news/sci-tech/iit_infineon_achieve_breakthrough_for_system-on-chip.php
EE Herald: http://www.eeherald.com/section/news/nw10000592.html
EE Times: http://www.eetimes.com/author.asp?section_id=36&doc_id=1284049
EE Times: http://www.eetimes.com/electronics-news/4083184/Infineon-Indian-researchers-claim-ESD-advance
Rediff: http://business.rediff.com/report/2009/apr/22/iit-achieves-breakthrough.htm

IISc Prof Wins a global award – India Express

IISc Prof Wins a global award – Hindu

IISc Prof Wins a global award – Global Indian

IISc Prof Wins a global award – Deccan Herald

IISc Faculty Devises technology to Shrink Power Elec Sys – Deccan Herald

IEEE EDS Early Career Award – IEEE

FinTEFT For Efficient Mobile Systems – Indian Express

FinTEFT For Efficient Mobile Systems – Bangalore Mirror

EDS Newsletter – April 2016 – EDS Award

BM-Graphene

DNA

Graphene

IE

MIT

SF

Science Outreach Through Invited Talks
(Other than peer reviewed presentations)

  1. “A Roadmap for Disruptive Applications & Heterogeneous Integration using 2-Dimensional Materials: State-of-the-Art and Technological Challenges”
      • Invited Talk, ASML, Veldhoven, Netherlands
      • Invited Talk, IMEC, Leuven, Belgium
      • Invited Talk, Recent Progress in Graphene and 2D materials Research (RPGR), 2023
      • 2023 NANOscientific Symposium Asia, Keynote Talk
      • 2023 International ESD Workshop & IEEE IRPS, Keynote Talk
      • IEEE Distinguished Lecture, IEEE EDS Malaysia Chapter
      • IEEE Distinguished Lecture, IEEE EDS IIT Roorkee Chapter
      • 2023, Heights Researcher’s Fest, University of Kerala (Trivandrum)
      • Invited Talk, IISER Thiruvananthapuram
  2. “The Future of World Electronics and the Possible Role India Can Play”
      • Distinguished Lecture, IEEE Sensors Council, NIT Jodhpur
      • Shrimati Indira Gandhi College, Tiruchirappalli
      • Bangalore Nano, March 2022
      • IIT Indore, March 2022
      • IIT Patna, Dec 2021
      • Distinguished Lecture, IEEE SJC EDS Chapter, Oct. 2021
      • IIIT Kancheepuram, Oct. 2021
      • TBI CPDMED CEFC Design Manufacturing and Entrepreneurship Series, Aug. 2021
      • Distinguished Lecture, IEEE CAS Chapter, Feb. 2021
      • Distinguished Lecture, NIT Jalandhar, Sep. 2020
      • Distinguished Lecture, IEEE Bangalore Section, June 2020
      • IEEE Mini-Colloquium, Delhi University, Sep. 6th 2019
      • School of Physics at the IISER, Thiruvananthapuram, August 24th 2019
      • Workshop on Microelectronics and Information Security, SSPL, Ministry of Defense, Oct. 2018
      • 41st Annual event of KSCST (August 12th 2018)
      • Innovation Bazar, Western Digital (July 6th 2018)
      • IEEE Talk, Madras Chapter (Dec 26th 2017)
      • SSPL, DRDO (Oct. 2017)
      • IEEE Region – 10 Golden Jubilee Event, August 5th, 2017 (Key Note Talk)
      • 51st Computer Society of India Conference (Memorial Talk, Jan. 24th 2016)
      • IEEE Golden Jubilee Congress (August 2016)
      • IISc EECS Symposium (Feb 2016)
  3. Gallium Nitride Electronics: Design and Reliability / e-mode HEMTs / Physics of Dynamic Ron”
      • Invited Talk, NXP, Nijmegen, Netherlands, Oct. 2023
      • Invited Talk, Nexperia, Munic, Germany, Oct. 2023
      • IEEE Talk, UCLA, USA, April, 2023
      • Invited Talk, XXII International Workshop on Physics of Semiconductor Devices (IWPSD), 2023
      • Indo-French Workshop, IIT Madras, Feb, 2023
      • GaN Marathon 2022, Venice, Italy, June, 2022
      • IWPSD – Invited Talk, Dec, 2021
      • 5th IEEE ICEE – Invited Talk, Dec, 2020
      • University of Padova, Padova, Italy, July, 2018)
      • Infineon Technology, Villach, Austria, July, 2018)
      • Online webinar organized by ESD Association USA, telecasted globally on 29th Nov. 2017.
      • Invited Talk, IWPSD, Dec. 2017
      • Invited Talk, ITC-India, July 2017
      • Invited Talk, ICYRAM-2016, Dec. 14th 2016
      • Invited Talk, Texas Instruments, Dallas, April, 2017
      • Invited Talk, Semiconductor Complex Limited (SCL), Department of Space, May 2017
      • IEEE Conference, July 11th, 2017
      • International Conference on Emerging Electronics, Dec. 5th 2014
  4. “Atomic Orbital Overlap Engineering for 3D-2D Contacts & Record High-Performance 2D Transistors”
      • Distinguished Lecture, IIIT Kanchipuram, Feb 22nd, 2023
      • IIT Madras, Feb 21st, 2023
      • NIT Jaipur, Feb 13th, 2023
      • ASET Colloquium Talk, TIFR, Mumbai, July 2022
      • DST Workshop, INST Mohali, August 2022
      • Distinguished Lecture, IIT BHU, August 2022
      • LIT Talk, IIT Bombay, July 2022
      • Invited talk at IWPSD – Dec 2019
      • IEEE ICEE, IIT Delhi, Nov. 2020
      • University of Budweiser, Munich, Germany, July 4th 2018
      • ISIF, Dec, 2017
      • IEEE International Conference on Emerging Electronics, Dec. 27th 2016
      • IIT Delhi, Jan 9th 2017
      • IIT Kanpur, Jan 10th 2017
  5. “Why Ph.D.? – Breaking the myths and misconceptions about Ph.D. and a guide to becoming a successful researcher”
      • Public Lecture, IIT Roorkee
      • 2023, Heights Researcher’s Fest, University of Kerala (Trivandrum)
      • Public Lecture, IISER Thiruvananthapuram
      • Public Lecture, IIIT Kanchipuram
      • Public Lecture, IIT Madras
      • Public Lecture, NIT Jaipur
  6. New Insights into ESD and HV Phenomena & ESD/HV Design Approaches in Silicon Technology Nodes
      • X-FAB, Erfurt, Germany
      • NXP, Nijmegen, Netherlands
      • Nexperia, Nijmegen, Netherlands
      • Infineon, Munich, Germany
      • Intel, Munich, Germany
      • Analog Device, USA
  7. “On-Chip ESD Devices and Circuits: Essentials and Research Opportunities”
      • 3rd India ESD Workshop, Feb 25th, 2019
      • 2nd India ESD Workshop, March 17th, 2017
      • 1st India ESD Workshop, Feb 26th, 2016
      • IIT Gandhinagar, Dec. 31st 2015
      • Semiconductor Complex Limited (SCL), Department of Space, July 1st 2015
      • EE Department, IIT Madras, July 2014
      • Texas Instruments Bangalore, India, April 2014
      • CRL Bangalore, Feb. 2014
      • Fifth Electrical Sciences Symposium, IISc Bangalore, Feb. 2014
  8. “ESD Design Essentials”, Bangalore, 8th and 9th 2015
      • ESD Device Physics
      • On-Chip ESD (Circuit) Design
      • CDM Phenomena and Protection Design
      • Latch-up
  9. “How Experimental and Computational Probes Enabled Development of (India’s First) GaN Based Power Transistor and Diode Technologies”
      • The Third Indian Materials Conclave and the 32nd Annual General Meeting of MRSI, Dec 2021
      • IWPSD, IIT Delhi, Dec 2021
      • IEEE ICEE, IIT Delhi, Nov. 2020
  10. “Should India Buy a Fab” / “India’s Race for Nanomanufacturing”
      • Bangalore Nano, March 2022
      • World Congress on Micro Nano Manufacturing, IIT Bombay, Sep. 2021
      • VAIBHAV Summit, Oct. 2020
  11. “ESD Device Physics of Advance and Beyond CMOS Devices”
      • Intel Corp., Munich, Germany (July 27th 2018)
      • Infineon Technology, Munich, Germany (July 28th 2018)
      • Intel Corp., Portland, USA (Sep 19th 2018)
      • NXP, Nijmegen, Netherlands (June 29th, 2018)
  12. “Performance & Reliability Co-Design Approach for High Voltage LDMOS Devices”
      • Infineon Technology, Munich and Kuching, Oct. 2020
      • NXP, Nijmegen, Netherlands (June 29th, 2018)
      • Semiconductor Complex Limited (SCL), Department of Space, July 2nd 2015
      • ANURAG, DRDO, Feb 2017
      • LRDE, DRDO, Feb 2017
  13. How Wide Bandgap Semiconductors Like GaN Can Transform Power Electronics Industry?”, Keynote Talk, Cyient Power Electronics Conference, Oct. 2021
  14. “THz Electronics Opportunities and R&D Challenges”, Invited talk in the International Workshop on THz Technology, IIT Delhi, Sep 21st 2019
  15. “Towards the end of Moore’s Law: Options and Challenges Beyond Advanced FinFET Technologies to Sustain CMOS ULSI”, Tutorial talk at IWPSD – Dec 2019
  16. “Defect Assisted Atomic Orbital Overlap Engineering for Metal – 2D Material’s Contacts & Record High Performance Transistors”
    • Invited talk at IWPSD – Dec 2019
    • IEEE ICEE, IIT Delhi, Nov. 2020
  17. “ESD Reliability and Physics of Carbon Electronics”, International ESD Workshop, USA, 1st April, 2019
  18. “ESD Robust LDMOS Design Essentials” Online webinar organized by ESD Association USA, telecasted globally in Nov. 2014.
  19. “IC and System Design for Electrostatic Discharge Protection”, IEEE INDICON, Dec. 2013
  20. “Drain extended MOS device design and reliability challenges” IWPSD Dec. 2013
  21. “A Review on the ESD Robustness of Drain Extended MOS Devices” International ESD workshop, May 20, 2013, Warrenton, VA, USA
  22. “3D TCAD Based approach for ESD failure analysis“, Infineon Technologies, AG, Munich (Germany), June 2010.
  23. “Reliability aware I/O design for sub 45nm node CMOS technology” IWPSD-2009, 18th Dec, 2009.
  24. “Benchmarking the device performance at sub 22 nm node technologies using an SoC framework“, IWSG-2009, 3rd Dec 2009.
  25. “3D filament behavior of various HV DeMOS devices under ESD condition” University of California (SB), USA, 4th Sep, 2009.
  26. “Filament behavior of various DeMOS devices“, Technical University of Vienna, Austria, 8th Oct 2008.
  27. “ESD optimization of DeMOS devices“, Infineon Technologies, AG, Munich (Germany), 6th Oct 2008.
  28. “Mixed signal and hot carrier performance of various DeMOS devices” Infineon Technologies, AG, Munich (Germany), 3rd May 2008

Patents

Granted Patents (#1 – #31 are granted in US, #1 – #20 granted in two or more than two countries, #32 – #39 granted in India):  

  1. Rajesh Thakkar, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, “Operational Amplifier Having Improved Slew Rate ” United States Patent (03-01-2012) 8,089,314 (Also filed/granted in other countries, India: 542/MUM/2010, European Patent: EP2543141; Chinese Patent: CN102474230; and PCT: WO2011107824)
  2. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “Nonvolatile floating gate analog memory cell”, United States Patent (07-05-2013) 8,436,413 (Also filed/granted in other countries, Indian Patent No 258773; and PCT: WO2010046922.)
  3. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei,” Semiconductor devices with trench isolations”, United States Patent (17-01-2012) 8,097,930 (Also granted in Germany, Patent No: DE102009034405)
  4. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-effect device and manufacturing method thereof”, United States Patent (15-01-2013) 8,354,710 (Also granted in Germany, Patent No: DE102009030086)
  5. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, Ramgopal Rao, Christian Russ, “Device and method for coupling first and second device portions”, United States Patent (04-06-2013) 8,455,947  (Also granted in Germany, Patent No: DE102010000355)
  6. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain extended field effect transistors and methods of formation thereof”, United States Patent (17-09-2013) 8,536,648  (Also granted in Germany, Patent No: DE102012100767)
  7. Mayank Shrivastava and Harald Gossner, “Drain extended MOS device for Bulk FinFET technology”, United States Patent (14-01-2014) 8,629,420 (Also granted in Germany, Patent No: DE102013106152; Taiwan, Patent No: TW201411844 and in China, Patent No: CN103531633)
  8. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Semiconductor devices and methods for manufacturing a semiconductor device”, United States Patent (04-02-2014) 8,643,090 (Also granted in Germany, Patent No: DE102010016000)
  9. Mayank Shrivastava, Christian Russ, Harald Gossner, “Low voltage ESD clamping using high voltage devices”, United States Patent (18-02-2014) 8,654,491 (Also granted in Germany, Patent No: DE102013103076; and in China, Patent No: CN107424988)
  10. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, “High voltage semiconductor devices”, United States Patent (04-03-2014) 8,664,720 (Also granted in Germany, Patent No: DE102011050958)
  11. Mayank Shrivastava, Christian Russ, Harald Gossner, “Selective current pumping to enhance low-voltage ESD clamping using high voltage devices”, United States Patent (25-03-2014) 8,681,461 (Also granted in Germany, Patent No: DE102013103076 and in China, Patent No: CN103367357)
  12. Mayank Shrivastava and Harald Gossner, “Silicon controlled rectifier (SCR) device for bulk FinFET technology”, United States Patent (22-07-2014) 8,785,968 (Also granted in Taiwan, Patent No: TW201423957)
  13. Mayank Shrivastava, Christian Russ and Harald Gossner, “Tunable Fin-SCR for Robust ESD Protection”, United States Patent (24-02-2015) 8,963,201.
  14. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-Effect Device and Manufacturing Method Thereof”, United States Patent (19-05-2015) 9,035,375 (Also granted in Germany, Patent No: DE102009030086)
  15. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain Extended Field Effect Transistors and Methods of Formation Thereof”, United States Patent (21-07-2015) 9,087,892 (Also granted in Germany, Patent No: DE102012100767).
  16. Mayank Shrivastava and Christian Russ, “Semiconductor devices and arrangements for electrostatic (ESD) protection”, United States Patent (31-05-2016) 9,356,013.
  17. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, Ramgopal Rao, “Methods for manufacturing a semiconductor device”, United States Patent (14-06-2016) 9,368,573 (Also granted in Germany, Patent No: DE102010016000)
  18. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-effect device and manufacturing method thereof”, United States Patent (26-07-2016) 9,401,352 (Also granted in Germany, Patent No: DE102009030086)
  19. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, “High voltage semiconductor devices”, United States Patent (27-09-2016) 9,455,275. (Also granted in Germany, Patent No: DE102011050958).
  20. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain extended field effect transistors and methods of formation thereof”, United States Patent (09-05-2017) 9,647,069. (Also granted in Germany, Patent No: DE102012100767)
  21. Mayank Shrivastava, Christian Russ and Harald Gossner, “Tunable FIN-SCR for Robust ESD Protection”, United States Patent (28-03-2017) 9,608,098.
  22. Mayank Shrivastava and Christian Russ, “Semiconductor Devices And Arrangements Including Dummy Gates For Electrostatic Discharge Protection”, United States Patent No: (14-03-2017) 9,595,516.
  23. Mayank Shrivastava, Milova Paul, Christian Russ and Harald Gossner, “Non-planar Electrostatic Discharge (ESD) Protection Devices With Nano Heat Sinks”, US Patent No (11-06-2019): 10,319,662 (Indian Patent, Application No 201741003773, Filed on 1st Feb. 2017)
  24. Mayank Shrivastava, Milova Paul, Christian Russ and Harald Gossner, “Low Trigger and Holding Voltage Silicon Controlled Rectifier (SCR) For Non-Planar Technologies”, US Patent No (19-02-2019): 10,211,200 (Indian Patent, Application No 201741003772, Filed on 1st Feb. 2017)
  25. Mayank Shrivastava, Milova Paul and Harald Gossner, “Electrostatic Discharge (ESD) Protection Devices For ESD Robustness, Latch-Up and Hot Carrier Immunity”, US Patent No (19-11-2019): 10,483,258 (Indian Patent No. 376841)
  26. Milova Paul, Mayank Shrivastava, Sampath Kumar, Christian Russ and Harald Gossner, “Dual Fin Silicon Controlled Rectifier (SCR) Electrostatic Discharge (ESD) Protection Device”, US Patent No (21-04-2020): 10,629,586 (Indian Patent, Application No 201741003771, Filed on 1st Feb. 2017)
  27. Mayank Shrivastava, Recess Gate Superjunction High-electron-mobility transistor (HEMT)”, US Patent No (02-02-2020): 10,553,712 (Indian Patent No: 522306,  Granted on 08th March 2024.)
  28. Mayank Shrivastava, Milova Paul and Harald Gossner, “FinFET SCR With SCR Implant Under Anode And Cathode Junctions”, US Patent No (04-02-2020): 10,535,762, (Indian Patent, Application No 201741006746, Filed on 25th Feb. 2017)
  29. Mayank Shrivastava, Sayak Dutta Gupta, Ankit Soni, Srinivasan Raghavan and Navakanta Bhat, “Enhancement Mode High Electron Mobility Transistor (HEMT)”, US Patent No (17-11-2020): 10,840,348 (Indian Patent Application 201741030570, August 2017)
  30. Rohit Soman, Ankit Soni, Mayank Shrivastava, S. Raghavan and Navakanta Bhat “High Electron Mobility Transistor (HEMT) with Resurf Junction”, US Patent Application No: US20200227543 A1  (Indian Patent No: 310947)
  31. Mayank Shrivastava and Vipin Joshi, “Doping and Trap Profile Engineering in GaN Buffer To Maximize AlGaN/GaN HEMT Epi Stack Breakdown Voltage”, US Patent No (08-06-2021):11,031,493 (Indian Patent Application 201841020899, Filled on June 5th 2019)
  32. Ankit Soni and Mayank Shrivastava, “Novel Drain Connected Field Plate HEMT Designs having Improved Performance”, Indian Patent No: 503229 (Filing Date: 9th March 2020, Grant Date: 25th January 2024)
  33. Ankit Soni and Mayank Shrivastava, “High Electron Mobility Transistor with improved performance and linearity”, Indian Patent No: 510450 (Filed on 29th December 2019, Grant Date: 13th February 2024)
  34. Ansh, Hemanjaneyulu Kuruva and Mayank Shrivastava, “Methods of Manufacturing 2-Dimentional Semiconductor Transistors”, Indian Patent No. 482722, (Filed: September 2017, Grant Date: 14/12/2023)
  35. N. S. Kranthi, K. Hemanjaneyulu, and Mayank Shrivastava, “A Field Effect Transistor (FET) with Improved Failure Threshold”, Indian Patent No. 441063 (Filed: July 2017, Grant Date: 28/07/2023)
  36. Mayank Shrivastava, “Drain extended Tunnel FET”, US Patent Pending, Application No: US2021119044 (A1), Filed on: 23-Feb-17 (Indian Patent No: 470520, Filed on Feb 26th 2016, Grant Date: 20/11/2023)
  37. Mayank Shrivastava and Kuruva Hemanjaneyulu “Fin enabled area scaled tunnel field Effect transistor”, Patent No: 364758 (Filed on May 26th 2015, Grant Date: 16/04/2021).
  38. Mayank Shrivastava, “Miniaturized, High Power Density Power Electronic System on a Chip”, Indian Patent No: 417131 (Filed on March 19th 2015, Grant Date: 06/01/2023).
  39. Mayank Shrivastava, “A Flexible, Adaptive Neuromorphic Synaptic Chip” Indian Patent No: 512480 (Filed on 17th July 2019, Grant Date: 20th February 2024)

Filed, yet to be granted:

  1. Rasik Rashid Malik and Mayank Shrivastava, “GATE METALLIZATION DESIGN FOR e-MODE GaN HEMTS”, Indian Patent Application No: 202441032159, Filing Date: 23rd April 2024
  2. Mehak Ashraf Mir and Mayank Shrivastava, “A SURFACE PASSIVATION FOR A HIGH ELECTRON MOBILITY TRANSISTOR”, Indian Patent Application No: 202441029855, Filing Date: 12 April 2024
  3. Monishmurali M and Mayank Shrivastava, “Low Capacitance FINFET SCR”, Application No. 202341060124, filed on 07-Sep-2023
  4. Mayank Shrivastava and Rasik Rashid Malik, “Method of Making High Robustness E-mode High Electron Mobility Transistor”, Application No. 202341059981, filed on 06-Sep-2023
  5. Utpreksh Patbhaje and Mayank Shrivastava, “Two-Dimensional (2D) Transition Metal Dichalcogenide Based Analog Memory Device”, Application No. 202341059978, filed on 06-Sep-2023
  6. Mayank Shrivastava and Rasik Rashid Malik, “Method for High Threshold Voltage and High Breakdown Gate Stack in p-GaN Gate e-mode HEMTs”, Application No. 202341059979, filed on 06-Sep-2023
  7. Jeevesh Kuma, Aadil Bashir Dar and Mayank Shrivastava, “Heat Spreader for System on Chip Device”, Application No. 202341060385, filed on 08-Sep-2023
  8. Mayank Shrivastava and Rasik Rashid Malik, “Method to Tune Gate Work Function in p-GaN Gate e-mode HEMTs”, Application No. 202341059980, filed on 06-Sep-2023
  9. Mayank Shrivastava and Rasik Rashid Malik, “A Method for Multiple Passivation Approach in p-GaN Gate e-Mode HEMTs”, Application No. 202341059983, filed on 06-Sep-2023
  10. Mayank Shrivastava and Anand Kumar Rai, “Doping and Activation Scheme for 2D Semiconductors”, Application No. 202341059982, filed on 06-Sep-2023
  11. Rasik Rashid and Mayank Shrivastava, “High Electron Mobility Transistor Device”, Indian Patent Application No: 202241038091, Filing Date: 1st July 2023
  12. Jatin and Mayank Shrivastava, “Nanosheet Drain Extended MOSFET”, Indian Patent Application No: 202341007382, Filing Date: 6th February 2023
  13. Jatin and Mayank Shrivastava, “Metal Oxide Semiconductor Device Architecture with Uniform Finger Turn On And Method Thereof”, Indian Patent Application No: 202341026588, Filing Date: 10th April 2023
  14. Adil Meersha, Mamta Khaneja and Mayank Shrivastava, A Method of Depositing Gate Dielectric on a 2D Material, Indian Patent Application: 202111057162, Dec. 8th, 2021.
  15. Adil Meersha, Mohan Lal and Mayank Shrivastava, Multilayer Graphene Contact for Monolayer Graphene Channel, Indian Patent Application: 202111057161, Dec. 8th, 2021.
  16. Adil Meersha, Jaswant Singh Rawat and Mayank Shrivastava, Method to Selectively Etch h-BN, Indian Patent Application: 20111057160, Dec. 8th, 2021.
  17. Adil Meersha, Prashant Kumar and Mayank Shrivastava, Graphene Transistor with Defected Graphene Layer, Indian Patent Application: 20111057163, Dec. 8th, 2021.
  18. Monishmurali M and Mayank Shrivastava, “Fin-Based SCR Architectures Having Distributed Current Configuration and Enhanced ESD Protection”, Indian Patent Application No: 202041011502, Filing Date: March 17th, 2020
     

List of Publications

Overall, 250 publications. 215 publications in IEEE journals (or better) and peer reviewed IEEE conferences of high repute. 55 publications in the IEEE International Electron Devices Meeting (IEDM) & the IEEE International Reliability Physics Symposium (IRPS), which are the two most prestigious conferences for Electron Devices.

Books, Book chapters and Technical Briefs

  1. Chapter titled “Towards Drain extended FinFETs for SoC applications” in book “Toward Quantum FinFET”, edited by Weihua Han and Zhiming M. Wang, Springer, Dec. 2013, ISBN 978-3-319-02021-1.
  2. Mayank Shrivastava and V. Ramgopal Rao, “Tunnel Field Effect Transistors”, Present, Past and Future, Technical Brief appeared in the IEEE EDS Newsletters, July 2016 (Cover page article).


Peer Reviewed International Journals

  1. M. A. Mir, V. Joshi, R. R. Chaudhuri, M. A. Munshi, R. R. Malik and M. Shrivastava, “Physical Insights Into the Drain Current Injection-Induced Device Instabilities in AlGaN/GaN HEMTs,” in IEEE Transactions on Electron Devices, doi: 10.1109/TED.2024.3427097.
  2. Anand Kumar Rai, Asif A. Shah, Jeevesh Kumar, Sumana Chattaraj, Aadil Bashir Dar, Utpreksh Patbhaje, and Mayank Shrivastava, “Contact Doping, Defect Passivation and Performance Enhancement of MoS2 FETs via Fluorine Ion Introduction in Contacts & its Cyclic Field-Assisted Activation”, ACS Nano 2024, 18, 8, 6215–6228. DOI: https://doi.org/10.1021/acsnano.3c09428
  3. Jatin, M. Monishmurali, and Mayank Shrivastava, “On the Multi-Finger Turn-on Instability in Drain Extended Vertically Stacked Nanosheet FETs Under ESD Stress Conditions”, IEEE Transactions on Electron Devices, Volume: 71, Issue: 2, February 2024. DOI: 10.1109/TED.2023.3347708
  4. Kuruva Hemanjaneyulu, Jeevesh Kumar, and Mayank Shrivastava, “Enhanced Carrier Injection Across S/D Contacts in Selenium Based TMD FETs Using KI & Metal Induced Gap-States Engineering”, IEEE Journal of Electron Devices, Vol. 12, Jan. 2024, pp: 46-50. DOI: 10.1109/JEDS.2023.3345020
  5. Asif Shah, J. Kumar, A. B. Dar and Mayank Shrivastava, “Unveiling the Interfacial Behavior of Au Contacted MoS2 Atomristor and the Role of Point Defects,” in IEEE Transactions on Electron Devices, vol. 70, no. 12, pp. 6622-6629, Dec. 2023, DOI: 10.1109/TED.2023.3325800.
  6. Vipin Joshi, R. Roy Chaudhuri, S. Dutta Gupta and Mayank Shrivastava, “Impact of Buffer Capacitance-Induced Trap Charging on Electric Field Distribution and Breakdown Voltage of AlGaN/GaN HEMTs on Carbon-Doped GaN-on-Si,” in IEEE Transactions on Electron Devices, vol. 70, no. 12, pp. 6465-6472, Dec. 2023, DOI: 10.1109/TED.2023.3321281.
  7. R. R. Chaudhuri, V. Joshi, R. R. Malik and Mayank Shrivastava, “Physical Insights Into the Lattice Temperature Dependent Evolution of Hot Electron Distribution in GaN HEMTs on C-Doped GaN-on-Si,” in IEEE Transactions on Electron Devices, DOI: 10.1109/TED.2023.3326111.
  8. R. R. Malik, V. Joshi, R. R. Chaudhuri, S. D. Gupta and Mayank Shrivastava, “Reverse Bias Stress-Induced Turn-On Voltage Shift in Recessed AlGaN/GaN Schottky Barrier Diodes,” in IEEE Transactions on Electron Devices, vol. 70, no. 12, pp. 6211-6216, Dec. 2023, DOI: 10.1109/TED.2023.3321864.
  9. R. R. Chaudhuri, A. Gupta, V. Joshi, R. R. Malik, S. D. Gupta and Mayank Shrivastava, “Impact of Channel Electric Field Profile Evolution on Nanosecond Timescale Cyclic Stress-Induced Dynamic RON Behavior in AlGaN/GaN HEMTs—Part II,” in IEEE Transactions on Electron Devices, vol. 70, no. 12, pp. 6183-6189, Dec. 2023, DOI: 10.1109/TED.2023.3300652.
  10. R. Roy Chaudhuri, A. Gupta, V. Joshi, R. R. Malik, S. D. Gupta and Mayank Shrivastava, “Physical Insights Into Nano-Second Time Scale Cyclic Stress Induced Dynamic Ron Behavior in AlGaN/GaN HEMTs—Part I,” in IEEE Transactions on Electron Devices, vol. 70, no. 12, pp. 6175-6182, Dec. 2023, DOI: 10.1109/TED.2023.3323439.
  11. Monish Monishmurali and Mayank Shrivastava, “Enhancing ESD Performance of FinSCRs: Engineering Schemes to Address Current Localization and Failure Current Scalability,” in IEEE Transactions on Electron Devices, vol. 70, no. 8, pp. 4067-4074, Aug. 2023, DOI: 10.1109/TED.2023.3292070.
  12. Vipin Joshi, R. Roy Chaudhuri, S. Dutta Gupta and Mayank Shrivastava, “Physical Insights Into Electron Trapping Mechanism in the Carbon-Doped GaN Buffer in AlGaN/GaN HEMTs and Its Impact on Dynamic On-Resistance,” in IEEE Transactions on Electron Devices, vol. 70, no. 6, pp. 3011-3018, June 2023, DOI: 10.1109/TED.2023.3269409.
  13. Jeevesh Kumar, Mayank Shrivastava, “Role of Chalcogen Defect Introducing Metal-Induced Gap States and Its Implications for Metal-TMDs’ Interface Chemistry,” ACS Omega, 2023 Mar 9;8(11):10176-10184, DOI: 10.1021/acsomega.2c07489.
  14. Adil Meersha, J. Kumar, A. Mishra, H. B. Variar and Mayank Shrivastava, “Vacancy Assisted Bilayer Graphene Contact for Monolayer Graphene Channel Devices,” in IEEE Electron Device Letters, vol. 44, no. 4, pp. 666-669, April 2023, DOI: 10.1109/LED.2023.3250329.
  15. Jeevesh Kumar, Utpreksh Patbhaje, Mayank Shrivastava, “Breathing Mode’s Temperature Coefficient Estimation and Interlayer Phonon Scattering Model of Few-Layer Phosphorene“, ACS Omega 2022 7 (48), 43462-43467 DOI: 10.1021/acsomega.2c03759
  16. Rajarshi Roy Chaudhuri, Sayak Dutta Gupta, Vipin Joshi, and Mayank Shrivastava, “Observations and Physical Insights into Time Dependent Hot Electron Current Confinement in AlGaN/GaN HEMTs on C-doped GaN Buffer,” IEEE Transactions on Electron Devices, Volume: 69, Issue: 12, Pages: 6602-6609, Dec 2022. DOI: 10.1109/TED.2022.3213627
  17. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri and Mayank Shrivastava, “Unique Role of Hot-Electron Induced Self-Heating in Determining Gate Stack Dependent Dynamic RON of AlGaN/GaN HEMTs under Semi-ON State”, IEEE Transactions on Electron Devices, Volume: 69, Issue:12, Pages: 6934-6939, Dec 2022. DOI: 10.1109/TED.2022.3212327
  18. Vipin Joshi, Sayak Dutta Gupta, Rajarshi Roy Chaudhuri and Mayank Shrivastava, “Interplay of Device Design and Carbon Doped GaN Buffer Parameters in Determining Dynamic RON in AlGaN/GaN HEMTs”, IEEE Transactions on Electron Devices, Volume: 69, Issue: 11, Pages: 6035-6042, Nov 2022. DOI: 10.1109/TED.2022.3209635
  19. Jeevesh Kumar, Utpreksh Patbhaje and Mayank Shrivastava, “Breathing Mode’s Temperature Coefficient Estimation and Interlayer Phonon Scattering Model of Few-layer Phosphorene”, ACS Omega, Volume: 7, Issue: 48, Pages: 43462–43467, Nov 2022. DOI: 10.1021/acsomega.2c03759
  20. Ansh and Mayank Shrivastava, “Nature of Electrically Induced Defects in CVD-grown Monolayer MoS2”, Nature Communications Materials, Volume: 4, Article: 8, Feb 2023. DOI: https://doi.org/10.1038/s43246-023-00333-y
  21. Ankit Soni and Mayank Shrivastava, “Implications of Various Charge Sources in AlGaN/GaN Epi-Stack on the Drain & Gate Connected Field Plate Design in HEMTs,” in IEEE Access, Vol. 10, pp. 74533-74541, 2022, DOI: 10.1109/ACCESS.2022.3190484.
  22. Jeevesh Kumar, Utpreksh Patbhaje and Mayank Shrivastava, “Role of Channel Inversion in Ambient Degradation of Phosphorene FETs”, IEEE Transactions on Electron Devices, Volume: 69, Issue: 6, June 2022. DOI: 10.1109/TED.2022.3171504
  23. N. K. Kranthi, James Di Sarro, Krishna Rajagopal, Hans Kunz, Rajkumar Sankaralingam, Gianluca Boselli, and Mayank Shrivastava, “Unique Rise Time Sensitivity Leading to Air Discharge System Level ESD Failures in Bi-Directional High Voltage SCRs”, IEEE Transactions on Electron Devices, Volume: 69, Issue: 5, May 2022. DOI: 10.1109/TED.2022.3159281
  24. Kuruva Hemanjaneyulu, Adil Meersha, Jeevesh Kumar and Mayank Shrivastava, “Unveiling Unintentional Fluorine Doping in TMDs During the Reactive Ion Etching: Root Cause Analysis, Physical Insights, and Solution”, IEEE Transactions on Electron Devices, Volume: 69, Issue: 4, April 2022. DOI: 10.1109/TED.2022.3152459
  25. Hemanjaneyulu Kuruva, Jeevesh Kumar and Mayank Shrivastava, “Gaps in the Y-Function Method For Contact Resistance Extraction in 2D Few-Layer Transition Metal Dichalcogenide Back-Gated FETs”, IEEE Electron Device Letters, Volume: 43, Issue: 4, April 2022. DOI: 10.1109/LED.2022.3149410
  26. Aakanksha Mishra, Mayank Shrivastava and Ankur Gupta, “The Root Cause Behind a Peculiar Dual-Mode ON-State Breakdown in High Voltage LDMOS”, IEEE Transactions on Electron Devices, Volume: 69, Issue: 4, April 2022. DOI: 10.1109/TED.2022.3149236
  27. Jeevesh Kumar, Adil Meersha, Harsha Balakrishnan Variar, Abhishek Mishra and Mayank Shrivastava, “Carbon Vacancy Assisted Contact Resistance Engineering in Graphene FETs”, IEEE Transactions on Electron Devices, Volume: 69, Issue: 4, April 2022. DOI: 10.1109/TED.2022.3151033
  28. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri and Mayank Shrivastava, “Unique Gate Bias Dependence of Dynamic ON Resistance in MIS-gated AlGaN/GaN HEMTs & Its Dependence on Gate Control over the 2-DEG”, IEEE Transactions on Electron Devices, Volume: 69, Issue: 3, March 2022. DOI: 10.1109/TED.2022.3144378
  29. N. S. Kranthi, Gianluca Boselli and Mayank Shrivastava, “HV-LDMOS Device Engineering Insights for Moving Current Filament to Enhance ESD Robustness”, IEEE Transactions on Electron Devices, Volume: 69, Issue: 3, March 2022. DOI: 10.1109/TED.2022.3143073
  30. Jeevesh Kumar and Mayank Shrivastava, “First-Principles Molecular Dynamics Insight into Atomic Level Degradation Pathway of Phosphorene”, ACS Omega, Volume: 7, Issue: 1, 696–704, January 2022. DIO: https://doi.org/10.1021/acsomega.1c05353
  31. Ansh and Mayank Shrivastava, “Superior Resistance Switching in Monolayer MoS2 Channel Based Gated Binary Resistive RAM via Gate-Bias Dependence and a Unique Forming Process”, Journal of Physics D: Applied Physics, Volume 55, Number 8, Nov. 2021.
  32. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri and Mayank Shrivastava, “Part I: Physical Insights into Dynamic RON Behavior and a Unique Time Dependent Critical Stress Voltage in AlGaN/GaN HEMTs” IEEE Transaction of Electron Devices, Volume: 68, Issue: 11, Nov. 2021. DOI: 10.1109/TED.2021.3109847
  33. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri and Mayank Shrivastava, “Novel Surface Passivation Scheme by Using p-Type AlTiO to Mitigate Dynamic ON Resistance Behavior in AlGaN/GaN HEMTs – Part II”, IEEE Transaction of Electron Devices, Volume: 68, Issue: 11, Nov. 2021. DOI: 10.1109/TED.2021.3064531
  34. Mayank Shrivastava and V. Ramgopal Rao, “A Roadmap for Disruptive Applications & Heterogeneous Integration using 2-Dimensional Materials: State-of-the-Art and Technological Challenges”, ACS Nano Letters, 21, 15, 6359–6381, August 2021. DOI: https://doi.org/10.1021/acs.nanolett.1c00729
  35. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri and Mayank Shrivastava, “Observations Regarding Deep-Level States Causing p-Type Doping in AlTiO Gate & Positive Threshold Voltage Shift in AlGaN/GaN High Electron Mobility Transistors” Journal of Applied Physics 130, 015701 (2021). DOI: https://doi.org/10.1063/5.0053982
  36. Rajarshi Roy Chaudhuri, Vipin. Joshi, Sayak Dutta Gupta and Mayank Shrivastava, “On the Channel Hot-Electron’s Interaction with C-doped GaN Buffer and Resultant Gate Degradation in AlGaN/GaN HEMTs,” IEEE Transactions on Electron Devices, Volume: 68, Issue: 10, Oct. 2021. DOI: 10.1109/TED.2021.3102469
  37. N. K. Kranthi, James Di Sarro, Rajkumar Sankaralingam, Gianluca Boselli and Mayank Shrivastava, “System-Level IEC ESD failures in High Voltage DeNMOS-SCR: Physical Insights and Design Guidelines”, IEEE Transactions on Electron Devices, Volume: 68, Issue: 9, Sept. 2021. DOI: 10.1109/TED.2021.3100810
  38. Ankit Soni and Mayank Shrivastava, “Interplay of Various Charge Sources in AlGaN/GaN Epi-Stack Governing HEMT Breakdown”, IEEE Transaction of Electron Devices, Volume: 68, Issue: 5, May 2021. DOI: 10.1109/TED.2021.3068079
  39. Abhishek Mishra, Adil Meersha, N.K. Kranthi, Jeevesh Kumar, N.S. Veenadhari Bellamkonda, Harsha B. Variar and Mayank Shrivastava, “Unified Mechanism for Graphene FET’s Electro-Thermal Breakdown & its Implications on Safe Operating Limits”, IEEE Transaction of Electron Devices, Volume: 68, Issue: 5, May 2021. DOI: 10.1109/TED.2021.3068081
  40. Ankit Soni and Mayank Shrivastava, “Design Guidelines for Recessed Schottky Barrier AlN/GaN Diode for THz Applications”, IEEE Transaction of Electron Devices, Volume: 68, Issue: 5, May 2021, DOI: 10.1109/TED.2021.3064541
  41. Jeevesh Kumar, Ansh, Mayank Shrivastava, “Introduction of Near to Far Infrared Range Direct Band Gaps in Graphene: A First Principle Insight”, ACS Omega 2021, Vol. 6, Issue: 8, 5619–5626, Feb 2021. DOI: https://doi.org/10.1021/acsomega.0c06058
  42. Vipin Joshi, Sayak Dutta Gupta, Rajarshi Roy Chaudhuri and Mayank Shrivastava “Part-I: Physical Insights into the Impact of Surface Traps on Breakdown Characteristics of AlGaN/GaN HEMTs”, IEEE Transaction on Electron Device, Volume: 68, Issue: 1, Pages: 72-79, Jan 2021. DOI: 10.1109/TED.2020.3034561
  43. Vipin Joshi, Sayak Dutta Gupta, Rajarshi Roy Chaudhuri and Mayank Shrivastava “Interplay between Surface and Buffer Traps in Governing Breakdown Characteristics of AlGaN/GaN HEMTs – Part II”, IEEE Transaction on Electron Device, Volume: 68, Issue: 1, Pages: 80-87, Jan 2021. DOI: 10.1109/TED.2020.3034562
  44. Jeevesh Kumar, Ansh and Mayank Shrivastava, “Stone-Wales Defect Vacancy Assisted Enhanced Atomic Orbital Interactions Between Graphene & Ambient Gases: A First Principles Insight”, ACS Omega, Volume: 5, Issue: 48, Pages: 31281-31288, Dec 2020. DOI: https://doi.org/10.1021/acsomega.0c04729
  45. Bhawani Shankar, Ankit Soni, Srinivasan Raghavan and Mayank Shrivastava, “Trap Assisted and Stress Induced Safe Operating Area Limits of AlGaN/GaN HEMTs”, IEEE Transaction on Device and Materials reliability, Volume: 20, Issue: 4, Pages: 767-774, Dec 2020. DOI: 10.1109/TDMR.2020.3033522
  46. Ansh, Jeevesh Kumar, Gaurav Sheoran and Mayank Shrivastava, “Electrothermal Transport Induced Material Re-Configuration and Performance Degradation of CVD-Grown Monolayer MoS2 Transistors”, Nature (npj) 2D Materials and Applications, 4 (1), 1-11, Nov. 2020. DOI: https://doi.org/10.1038/s41699-020-00171-3
  47. Ankit Soni and Mayank Shrivastava, “Design Guidelines and Performance Trade-offs in Recessed AlGaN/GaN Schottky Barrier Diodes”, IEEE Transactions of Electron Devices, Volume: 67, Issue: 11, Pages:4834-4841, Nov 2020. DOI: 10.1109/TED.2020.3024354
  48. B. Sampath Kumar, Ajay Singh, Milova Paul, Jhnanesh Somayaji, Harald Gossner and Mayank Shrivastava, “Device, Circuit, and Reliability Assessment of Drain-Extended FinFETs for Sub-14 nm System on Chip Applications”, Transactions on Electron Devices, Volume: 67, Issue: 11, Pages:4728-4735, Nov 2020. DOI: 10.1109/TED.2020.3020904
  49. Rajat Sinha, Prasenjit Bhattacharya, Sanjiv Sambandan and Mayank Shrivastava, “Nano-second timescale drain voltage induced electrical instabilities in hydrogenated amorphous silicon thin film transistors”, Japanese Journal of Applied Physics , Volume: 59, Issue: 7, Pages:074004, July 2020. DOI: https://doi.org/10.35848/1347-4065/ab9ef5
  50. Bhawani Shankar, Ankit Soni, Sayak Dutta Gupta, Swati Shikha, Sandeep Singh, Srinivasan Raghavan and Mayank Shrivastava, “Time Dependent Shift in SOA boundary and Early Breakdown of Epi-Stack in AlGaN/ GaN HEMTs Under Fast Cyclic Transient Stress”, IEEE Transactions on Device and Material Reliability, Volume: 20, Issue: 3, Pages:562-569, July 2020. DOI: 10.1109/TDMR.2020.3007128
  51. Milova Paul, Sampath B, Harald Gossner and Mayank Shrivastava, “Engineering Schemes for Bulk FinFET to Simultaneously Improve ESD/Latch-Up Behavior and Hot Carrier Reliability”, IEEE Transaction of Electron Devices, Volume: 67, Issue: 7, Pages:2745-2751, June 2020. DOI: 10.1109/TED.2020.2997757
  52. B. Sampath Kumar, Milova Paul, Harald Gossner and Mayank Shrivastava, “Physical Insights into the ESD Behavior of Drain Extended FinFETs (DeFinFETs) and Unique Current Filament Dynamics”, IEEE Transaction of Electron Devices, Volume: 67, Issue: 7, July 2020. DOI: 10.1109/TED.2020.2994170
  53. Andrew Naclerio Dmitri, N Zakharov, Jeevesh Kumar, Bridget R. Rogers, Cary L. Pint, Mayank Shrivastava and Piran R. Kidambi, “Visualizing Oxidation Mechanisms in Few-Layered Black Phosphorus via in-situ Transmission Electron Microscopy”, ACS Appl. Mater. Interfaces 2020, DOI: https://doi.org/10.1021/acsami.9b21116
  54. Bhawani Shankar, Ankit Soni and Mayank Shrivastava, “Electro-Thermo-Mechanical Reliability of Recessed Barrier AlGaN/GaN Schottky Diodes Under Pulse Switching Conditions”, IEEE Transaction of Electron Devices, Volume: 67, Issue:5, May 2020, pp: 2044-2051. DOI: 10.1109/TED.2020.2981568.
  55. Ankit Soni, Ajay Singh and Mayank Shrivastava, “Novel Drain Connected Field Plate GaN HEMT Designs for Improved VBD − RON Trade-off and RF PA Performance”, IEEE Transaction of Electron Devices, Volume: 67, Issue:4, APRIL 2020, pp: 1718-1725. DOI: 10.1109/TED.2020.2976636
  56. Bhawani Shankar, Srinivasan Raghavan and Mayank Shrivastava, “Distinct Failure Modes of AlGaN/GaN HEMTs under ESD Conditions” IEEE Transactions on Electron Devices, Volume: 67, Issue: 4, April 2020, pp: 1567 – 1574. DOI: 10.1109/TED.2020.2974508
  57. Ansh, Jeevesh Kumar, Gaurav Sheoran, Harsha Variar, Ravikesh Mishra, Hemanjaneyulu Kuruva, Adil Meersha, Abhishek Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Chalcogen Assisted Enhanced Atomic Orbital Interaction at TMDs–Metal Interface & Sulfur Passivation For Overall Performance Boost of 2D TMD FETs” IEEE Transactions on Electron Devices, Volume: 67, Issue:2, Feb. 2020, pp: 717-724. DOI: 10.1109/TED.2019.2958338.
  58. Ansh, Jeevesh. Kumar, Gaurav Sheoran, Ravikesh Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Selective Electron or Hole Conduction in Tungsten Diselenide (WSe2) Field Effect Transistors by Sulfur Assisted Metal Induced Gap State Engineering,” IEEE Transactions on Electron Devices, Volume: 67, Issue:1, Jan. 2020, pp: 383-388. DOI: 10.1109/TED.2019.2956781.
  59. M. Paul, B. Sampath Kumar, K. Karmel Nagothu, P. Singhal, H. Gossner and Mayank Shrivastava, “Drain-Extended FinFET With Embedded SCR (DeFinFET-SCR) for High-Voltage ESD Protection and Self-Protected Designs,” in IEEE Transactions on Electron Devices, vol. 66, no. 12, pp. 5072-5079, Dec. 2019. DOI: 10.1109/TED.2019.2949126.
  60. Prasenjit Bhattacharya, Rajat Sinha, Bikash Kumar Thakur, Virendra Parab, Mayank Shrivastava, Sanjiv Sambandan, “Adaptive Dielectric Thin Film Transistors-A Self-Configuring Device for Low Power Electrostatic Discharge Protection”, IEEE Electron Device Letters, Volume: 41, Issue: 1, Jan. 2020. DOI: 10.1109/LED.2019.2956838.
  61. Ankit Soni and Mayank Shrivastava, “Computational Modelling Based Device Design for Improved mmWave Performance and Linearity of GaN HEMTs,” IEEE Journal of the Electron Devices Society, Volume: 8, Issue:1, pp: 33-41, Jan 2020, DOI: 10.1109/JEDS.2019.2958915
  62. Rajat Sinha, Prasenjit Bhattacharya, Sanjiv Sambandan, and Mayank Shrivastava, “Nano-second timescale high-field phase transition in hydrogenated amorphous silicon.” Journal of Applied Physics 126, no. 13 (2019): 135706.
  63. Bhawani Shankar and Mayank Shrivastava, “Safe Operating Area of Polarization Super Junction GaN HEMTs & Diodes”, IEEE Transactions on Electron Devices, Volume: 66, Issue:9, Page(s): 3756-3763, September 2019, DOI: 10.1109/TED.2019.2926781.
  64. Ankit Soni, Swati Shikha and Mayank Shrivastava, “On the Role of Interface States in AlGaN/GaN Schottky Recessed Diodes: Physical Insights, Performance Tradeoff, and Engineering Guidelines”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 6, June 2019. DOI: 10.1109/TED.2019.2912783.
  65. Hemanjaneyulu Kuruva, Jeevesh Kumar and Mayank Shrivastava, “MoS2 Doping using Potassium Iodide for Reliable Contacts and Efficient FET Operation”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 7, July 2019, Page(s): 3224 – 3228. DOI: 10.1109/TED.2019.2916716.
  66. Sayak Dutta Gupta, Ankit Soni, Rudrarup Sengupta, Heena Khand, Bhawani Shankar, Nagboopathy Mohan, Srinivasan Raghavan, Navakanta Bhat, and Mayank Shrivastava, “Positive Threshold Voltage Shift in AlGaN/GaN HEMTs & E-mode Operation by AlxTi1-xO based Gate Stack Engineering”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 6, June 2019, Page(s): 2544 – 2550. DOI: 10.1109/TED.2019.2908960.
  67. Rajat Sinha, Prasenjit Bhattacharya, Tim Iben, Sanjeev Sambandan and Mayank Shrivastava, “ESD Reliability Study of a-Si:H Thin film Transistor Technology: Physical Insights and Technological Implications”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 6, June 2019. DOI: 10.1109/TED.2019.2913040.
  68. Bhawani Shankar, Rudrarup Sengupta, Sayak Dutta Gupta, Ankit Soni, Srinivasan Raghavan and Mayank Shrivastava, “ESD Behavior of AlGaN/GaN Schottky Diodes”, IEEE Transactions on Device and Materials Reliability, Volume: 19, Issue: 2, June 2019, Page(s): 437 – 444. DOI: 10.1109/TDMR.2019.2916846 (Invited Paper)
  69. Bhawani Shankar, Ankit Soni, Hareesh Chandrasekar, Srinivasan Raghavan and Mayank Shrivastava, “First Observations on the Trap Assisted Avalanche Instability and Safe Operating Area Concerns in AlGaN/GaN HEMTs”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 8, Aug. 2019, Page(s): 3433 – 3440. DOI: 10.1109/TED.2019.2919491.
  70. Bhawani Shankar and Mayank Shrivastava, “Unique ESD Behavior of AlGaN/GaN HEMTs”, IEEE Transactions on Device and Materials Reliability, Volume: 19, Issue: 2, June 2019, Page(s): 437 – 444. DOI: 10.1109/TDMR.2019.2916846.
  71. Nagothu Karmel Kranthi, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “ESD Behavior of Large Area CVD Graphene Transistors: Physical Insights and Technology Limitations”, IEEE Transactions on Electron Devices, Vol, 66, Issue: 1 , Pages: 743 – 751, Jan. 2019. (DOI: 10.1109/TED.2018.2877693)
  72. Vipin Joshi, Shree Prakash Tiwari, and Mayank Shrivastava, “Part-I: Physical insight into breakdown voltage improvement with Carbon doping in AlGaN/GaN HEMTs”, IEEE Transactions on Electron Devices, Vol., 66, Issue: 1 , Pages: 561 – 569, Jan. 2019. DOI: 10.1109/TED.2018.2878770
  73. Vipin Joshi, Shree Prakash Tiwari, and Mayank Shrivastava, ” Part II: Proposals to Independently Engineer Donor and Acceptor Trap Concentrations in GaN Buffer For Ultra High Breakdown AlGaN/GaN HEMTs”, IEEE Transactions on Electron Devices, Vol., 66, Issue: 1 , Pages: 570 – 577, Jan. 2019. (DOI: 10.1109/TED.2018.2878787)
  74. Milova Paul, B. Sampath Kumar, Christian Russ, Harald Gossner, Mayank Shrivastava, “Challenges & Physical Insights into the Design of Fin Based SCRs and a Novel Fin-SCR for Efficient On-Chip ESD Protection”, IEEE Transactions of Electron Devices, Vol, 65, Issue: 11, Pages: 4755 – 4763, Nov. 2018. (DOI: 10.1109/TED.2018.2869630)
  75. Milova Paul, Christian Russ, B Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Physics of Current Filamentation in ggNMOS Devices Under ESD Condition Revisited “, IEEE Transactions on Electron Devices, Vol, 65 , Issue: 7, pp. 2981 – 2989, July 2018. (DOI: 10.1109/TED.2018.2835831)
  76. Abhishek Mishra, Adil Meersha, Srinivasan Raghavan and Mayank Shrivastava, “Observing Non-equilibrium State of Transport through Graphene Channel at the Nano-Second Time Scale”, Applied Physics Letters, Vol. 111, Issue: 26, Pages: 263101-6, Dec. 2018. (DOI: 10.1063/1.5006258)
  77. B Sampath Kumar and Mayank Shrivastava, “Part I: On the Unification of Physics of Quasi-Saturation in LDMOS Devices”, IEEE Transactions on Electron Devices, Vol. 65, Issue: 1, Pages: 191-198, Jan. 2018. (DOI:10.1109/TED.2017.2777004)
  78. B Sampath Kumar and Mayank Shrivastava, “Part II: RF, ESD, HCI, SOA, and Self Heating Concerns in LDMOS Devices Versus Quasi Saturation”, IEEE Transactions on Electron Devices, Vol. 65, Issue: 1, Pages: 199-206, Jan. 2018. (DOI:10.1109/TED.2017.2732504)
  79. Abhishek Misra, Harald Gossner and Mayank Shrivastava, “ESD Behavior of MWCNT Interconnects – Part I: Observations and Insights”, IEEE Transactions on Device and Material Reliability, Vol. 17, Issue: 4, Pages: 600-607, Dec. 2017. (DOI:10.1109/TDMR.2017.2756924) (Invited Review Paper)
  80. Abhishek Misra and Mayank Shrivastava, “ESD Behavior of MWCNT Interconnects – Part II: Unique Current Conduction Mechanism”, IEEE Transactions on Device and Material Reliability, Vol. 17, Issue: 4, Pages: 608-615, Dec. 2017. (DOI:10.1109/TDMR.2017.2738701) (Invited Review Paper)
  81. Jhnanesh Somayaji, B.Sampath Kumar, M. S. Bhat, Mayank Shrivastava, “Performance and Reliability Codesign for Superjunction Drain Extended MOS Devices “, IEEE Transactions on Electron Devices, Vol, 64, Issue: 10 , Pages: 4175 – 4183, Oct. 2017.  (DOI: 10.1109/TED.2017.2733043 )
  82. Abhishek Mishra, Ravi Nandan, Srinivasan Raghavan and Mayank Shrivastava, ” Nano-second time resolved investigations on thermal implications of high-field transport through MWCNTs”, Applied Physics Letters, Vol. 110, Pages:  233111-6, May 2017. (https://doi.org/10.1063/1.4984282)
  83. Abhishek Mishra and Mayank Shrivastava, “Remote Joule Heating Assisted Carrier Transport in MWCNTs Probed at Nanosecond Time Scale”, Physical Chemistry Chemical Physics (PCCP) Journal of Royal Society of Chemistry, Vol. 18, Pages: 28932-28938, Jun 2016. (DOI:10.1039/C6CP04497B)
  84. Mayank Shrivastava, “Drain Extended Tunnel FET – A Novel High Voltage Device for Beyond FinFET System on Chip & Automotive Applications”, IEEE Transactions on Electron Devices, Vol. 64, Issue: 2, Pages: 481 – 487, Feb. 2017. (DOI:10.1109/TED.2016.2636920)
  85. Vipin Joshi, Ankit Soni, Shree Prakash Tiwari and Mayank Shrivastava, “A Comprehensive Computational Modeling Approach for AlGaN/GaN HEMTs”, IEEE Transactions on Nanotechnology, Vol. 15, Issue: 6, Pages: 947 – 955, Nov. 2016. (DOI:10.1109/TNANO.2016.2615645)
  86. Kranthi Nagothu and Mayank Shrivastava, “On the ESD Behavior of Tunnel FET Devices”, IEEE Transactions on Electron Devices, Vol. 64, Issue: 1, Pages: 28 – 36, Jan. 2017. (DOI:10.1109/TED.2016.2630079)
  87. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, Harald Gossner, and V. Ramgopal Rao, “On the Improved High-Frequency Linearity of Drain Extended MOS Devices”, IEEE Microwave and Wireless Components Letters, Vol. 26, Issue: 12, Pages: 999-1001, Dec. 2016. (DOI:10.1109/LMWC.2016.2623239)
  88. Peeyusha S. Swain, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “On the Geometrically Dependent Quasi-Saturation and gm Reduction in Advanced DeMOS Transistors”, IEEE Transactions on Electron Devices, Vol. 63, Issue: 4, Pages: 1621 1629, April 2016. (DOI:10.1109/TED.2016.2528282)
  89. Mayur Ghatge and Mayank Shrivastava, “Physical Insights On the Ambiguous Metal Graphene Interface and Proposal for Improved Contact Resistance”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 12, Pages: 4139- 4147, Dec 2015. (DOI:10.1109/TED.2015.2481507)
  90. Ketankumar H. Tailor, Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, and V. Ramgopal Rao, “Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain Extended PMOS Device”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 12, Pages: 4097- 4104, Dec 2015. (DOI:10.1109/TED.2015.2481899)
  91. Ketankumar H. Tailor, Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, and V. Ramgopal Rao, “Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device”, IEEE Transactions on Electron Devices, Vol. 62, Issue 12, Pages: 4105-4113, Dec 2015. (DOI:10.1109/TED.2015.2488683)
  92. Kuruva Hemanjaneyulu and Mayank Shrivastava, “Fin Enabled Area Scaled Tunnel FET”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 10, Pages: 3184- 3191, Oct. 2015. (DOI:10.1109/TED.2015.2469678)
  93. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Part II: A Fully Integrated RF PA in 28nm CMOS with Device Design for Optimized Performance and ESD Robustness”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 10, Pages: 3176-3183, Oct. 2015. (DOI:10.1109/TED.2015.2470109)
  94. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Part I: High Voltage MOS Device Design for Improved Static and RF Performance”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 10, Pages: 3168- 3175, Oct. 2015. (DOI:10.1109/TED.2015.2470117)
  95. Mayank Shrivastava, Neha Kulshrestha and Harald Gossner, “ESD Investigations of Multiwalled Carbon Nanotubes”, IEEE Transactions on Device and Material Reliability, Vol. 14, Issue: 1, Pages: 555 – 563, March, 2014. (DOI:10.1109/TDMR.2013.2288362)
  96. Peeyush Swain, Mayank Shrivastava, Harald Gossner, M. S. Baghini and V. Ramgopal Rao, “Device–Circuit Co-design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors”, IEEE Transactions on Electron Devices, Vol. 60, Issue: 11, Pages: 3827-3834, November, 2013. (DOI:10.1109/TED.2013.2283421)
  97. Anukool Rajoriya, Mayank Shrivastava, Harald Gossner, Thomas Schulz and V. Ramgopal Rao “Sub 0.5V Operation of Performance Driven Mobile Systems Based on Area Scaled Tunnel FET Devices”, IEEE Transactions on Electron Devices, Vol. 60, Issue: 8, Pages: 2626-2633, August, 2013. (DOI:10.1109/TED.2013.2270566)
  98. Mayank Shrivastava and Harald Gossner, “A Review on the ESD Reliability of Drain Extended MOS Devices”, IEEE Transactions on Device and Material Reliability, Vol. 12, Issue: 4, Pages: 615-625, December, 2012. (DOI:10.1109/TDMR.2012.2220358) (Invited Paper)
  99. Mayank Shrivastava, Harald Gossner and V. Ramgopal Rao, “A Novel Drain Extended FinFET Device for High Voltage High Speed Applications”, IEEE Electron Device Letters, Vol. 33, Issue: 10, Pages: 1432-1434, October, 2012. (DOI:10.1109/LED.2012.2206791)
  100. Mayank Shrivastava, Harald Gossner and Christian Russ, “A Novel Drain Extended NMOS Device with Spreading Filament under ESD Stress”, IEEE Electron Device Letters, Vol. 33, Issue: 9, Pages: 1294-1296,  September, 2012. (DOI:10.1109/LED.2012.2205553)
  101. Mayank Shrivastava, Manish Agrawal, Sunny Mahajan, Harald Gossner, Thomas Schulz, Dinesh Kumar Sharma, and V. Ramgopal Rao, “Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures”, IEEE Transactions on Electron Devices, Vol. 59, Issue: 5, Pages: 1353-1363, May, 2012. (DOI:10.1109/TED.2012.2188296)
  102. Mayank Shrivastava, Ruchit Mehta, Shashank Gupta, M. Shojaei Baghini, D. K. Sharma, Harald Gossner, T. Schulz, K. Arnim, W. Molzer, V. Ramgopal Rao, “Towards System On Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 6, Pages: 1597-1607, June, 2011. (DOI:10.1109/TED.2011.2123100)
  103. Ram Asra, Mayank Shrivastava, K. V. R. M. Murali, R. K. Pandey, Harald Gossner and V. Ramgopal Rao, “A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS-Comparable Performance”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 7, Pages: 1855-1863, July, 2011. (DOI:10.1109/TED.2011.2140322)
  104. Rajesh A. Thakker, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, and Mahesh B. Patil, ” A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs”, Microelectronics Journals, Vol. 42, Issue: 5, Pages: 758–765, May, 2011. (https://doi.org/10.1016/j.mejo.2011.01.010)
  105. Mayank Shrivastava, Ruchil Jain, M. Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “Solution towards the OFF state degradation in Drain extended MOS device”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 12,Pages:  3536-3539, December, 2010. (DOI:10.1109/TED.2010.2082549)
  106. Amitabh Chatterjee, Mayank Shrivastava, Harald Gossner, Sameer Pendharkar, Forrest Brewer, Charvaka Duvvury, ” An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device—Part I: Turn-On Behavior of the Parasitic Bipolar”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 2, Pages: 309 – 317, February, 2011. (DOI:10.1109/TED.2010.2093010)
  107. Amitabh Chatterjee, Mayank Shrivastava, Harald Gossner, Sameer Pendharkar, Forrest Brewer, Charvaka Duvvury, ” An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II(Two-Dimensional Study-Biasing & Comparison With NMOS)”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 2, Pages: 318 – 326, February, 2011. (DOI:10.1109/TED.2010.2093011)
  108. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Part I: On the Behavior of STI-Type DeNMOS Device under ESD Conditions”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 9, Pages: 2235 – 2242, September 2010. (DOI:10.1109/TED.2010.2055276)
  109. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 9, Pages: 2243 – 2250, September 2010. (DOI:10.1109/TED.2010.2055278)
  110. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “A novel bottom spacer FinFET structure for improved power-delay & short channel performance”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 6, Pages: 1287-1994, June 2010. (DOI:10.1109/TED.2010.2045686)
  111. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “PART I-“Mixed Signal Performance of Various High Voltage Drain Extended MOS devices” IEEE Transactions on Electron Devices, Vol. 57, Issue: 2, Pages: 448-457, Feb 2010. (DOI:10.1109/TED.2009.2036796)
  112. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “PART II-“A Novel scheme to optimize the mixed signal performance and hot carrier reliability of Drain Extended MOS devices” IEEE Transactions on Electron Devices, Vol. 57, Issue: 2, Pages: 458-465, Feb 2010. (DOI:10.1109/TED.2009.2036799)
  113. Mayank Shrivastava, Maryam Shojaei Baghini, A. Sachid, Dinesh Kumar Sharma, V. Ramgopal Rao, “A Novel and Robust Approach for Common Mode Feedback using IDDG FinFET”, IEEE Transactions on Electron Devices, Vol, 55, Issue: 11,Pages: 3274-3282, Nov 2008. (DOI:10.1109/TED.2008.2004475).

 

Peer Reviewed International IEEE Conferences with Proceedings (Available On IEEE Xplore)

  1. Jeevesh Kumar*, Aadil Bashir Dar*, Asif A. Shah, Amogh K. M., Sumana Chattaraj, Utpreksh Patbhaje, Anand K. Rai, Rupali Verma, and Mayank Shrivastava,” Breakthrough metal/graphene interface phonon engineering for reliable graphene based-heat spreaders”, 2024 IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, 14th – 18th April, 2024
  2. Rupali Verma, Utpreksh Patbhaje, Asif Altaf Shah, Aadil Bashir Dar, Rajarshi Roy Chaudhuri, Jeevesh Kumar, and Mayank Shrivastava, “Hot Carrier Dynamics and Electrical Breakdown Analysis in 2D Transition Metal Dichalcogenide FETs,” IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, 14th – 18th April, 2024
  3. Asif A. Shah, Rupali Verma, Rajarshi Roy Chaudhari, Aadil Bashir, Jeevesh Kumar, Anand Kumar Rai, Sumana Chattaraj, Mayank Shrivastava, “Electric field coupled molecular dynamics insights into anisotropic reliability issues of monolayer MoS2 based 2D FETs,” 2024 IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, 14th – 18th April, 2024
  4. Mehak A. Mir, A. Thakare, M. A. Munshi, V. Avinash, S. Wani, Z. Khan, R. Chaudhuri, S. Karthik, R. R. Malik, V. Joshi, Mayank Shrivastava “On the Role of Stress Engineering of Surface Passivation in Determining the Device Performance of AlGaN/GaN HEMTs,” 2024 IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, 14th – 18th April, 2024
  5. Rajarshi Roy Chaudhuri, Vipin Joshi, Rasik Rashid Malik, and Mayank Shrivastava, “Experimental Insights into the Role of Inter-valley and Defect Transitions of Hot Electrons in Determining Self-heating in AlGaN/GaN HEMTs,” 2024 IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, 14th – 18th April, 2024
  6. Mitesh Goyal, Raju Kumar, Mukesh Chaturvedi, Mahesh Vaidya, Mayank Shrivastava,” Current Filament Dynamics in ESD SCR in 28nm Technology,” 2024 IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, 14th – 18th April, 2024.
  7. Mitesh Goyal, Raju Kumar, Mukesh Chaturvedi, Mahesh Vaidya, Mayank Shrivastava, ” Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR,” 2024 IEEE International Reliability Physics Symposium (IRPS),  Dallas, Texas, USA, 14th – 18th April, 2024.
  8. Utpreksh Patbhaje, R. Verma, J. Kumar, Aadil B. Dar, Mayank Shrivastava, “Decoupling current and voltage mediated breakdown mechanism in CVD MoS2 FETs”, 2024 IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, 14th – 18th April, 2024.
  9. Purbasha Ray , Rupali Verma , Biswajeet Nayak, Suman Kumar Chakraborty, Mayank Shrivastava, and Prasana Kumar Sahoo “Probing the Origin of Photocurrent in 2D Bilayer MoSe2-WSe2 Lateral Heterostructure” Proceedings of 8th IEEE Electronic Devices Technology and Manufacturing (EDTM), 2024
  10. Biswajeet Nayak, Rupali Verma, Purbasha Ray, Suman Kumar Chakraborty, Mayank Shrivastava, and Prasana Kumar Sahoo “Robust Growth of Electronic Grade p-type Large Area 2D WSe2 and High-performance FET Devices” Proceedings of 8th IEEE Electronic Devices Technology and Manufacturing (EDTM), 2024
  11. M. A. Munshi, M. A. Mir, Vipin Joshi, R. R. Chaudhuri, Z. Khan, and Mayank Shrivastava, “Understanding Temperature Dependence of ESD Reliability in AlGaN/GaN HEMTs”, to appear in the proceedings of 44th EOSESD Symposium 2023, Octoder-2-4, 2023, Riverside USA.
  12. R. R. Malik, A. N. Shaji, Jayshree, Z. Khan, M. Bhattacharya, R. R. Chaudhuri, Vipin Joshi, and Mayank Shrivastava, “Interplay of Surface Passivation and Electric Field in Determining ESD Behaviour of p-GaN Gated AlGaN/GaN HEMTs”, to appear in the proceedings of 44th EOSESD Symposium 2023, Octoder-2-4, 2023, Riverside USA.
  13. Asif A. Shah, Jeevesh Kumar, Aadil Bashir Dar and Mayank Shrivastava, “Unveiling Root Cause of Defect Assisted Filamentation and Implication on Resistive Switching in MoS2 Atomristor”, to appear in the proceedings of the 7th IEEE Electron Devices Technology and Manufacturing (IEEE EDTM) Conference, 7th – 10th March, Seoul, Korea
  14. Monishmurali M, Nagothu Karmel Kranthi, Gianluca Boselli and Mayank Shrivastava, “Impact of Thin-oxide Gate on the On-Resistance of HV-PNP Under ESD Stress”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  15. Mehak Ashraf Mir, Vipin Joshi, Rajarshi Roy Chaudhuri, Mohammad Ateeb Munshi, Rasik Rashid Malik, and Mayank Shrivastava, “Dynamic Interplay of Surface and Buffer Traps in Determining Drain Current Injection induced Device Instability in OFF-state of AlGaN/GaN HEMTs”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  16. Rajarshi Roy Chaudhuri, Vipin Joshi, A. Gupta, T. Joshi, R. R. Malik, M. A. Mir, S. D. Gupta and Mayank Shrivastava, “Unique Lattice Temperature Dependent Evolution of Hot Electron Distribution in GaN HEMTs on C-doped GaN Buffer and its Reliability Consequences”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  17. Utpreksh Patbhaje, Rupali Verma, Jeevesh Kumar, Ansh and Mayank Shrivastava, “Unveiling Field Driven Performance Unreliabilities Governed by Channel Dynamics in MoSe2 FETs”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  18. Aakanksha Mishra, B. Sampath Kumar, Monishmurali M, Shaik Ahamed Suzaad, Shubham Kumar, Kiran Pote Sanjay, Amit Kumar Singh, Ankur Gupta, and Mayank Shrivastava, “Extremely Large Breakdown to Snapback Voltage Offser (Vt1>>VBD): Another Way to Improve ESD Resilience of LDMOS Devices”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  19. Jatin, Monishmurali M and Mayank Shrivastava, “Multi-finger turn-on: A potential cause of premature failure in Drain Extended HV Nanosheet Devices”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  20. Harsha B Variar, Satendra Kumar Gautam, Ashita Kumar, Amogh K M, Juan Luo, Ning Shi, David Marreiro, Shekar Mallikarjunaswamy and Mayank Shrivastava, “Engineering Custom TLP Characteristic Using a SCR-Diode Series ESD Protection Concept”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  21. Satendra Kumar Gautam, Harsha B Variar, Juan Luo, Ning Shi, David Marreiro, Shekar Mallikarjunaswamy, Mayank Shrivastava, “3D Approaches to Engineer DC & TLP Holding Voltage of SCR”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  22. Harsh Raj, Vipin Joshi, Rajarshi Roy Chaudhuri, Rasik Rashid Malik, and Mayank Shrivastava, “Physical Insights into the DC and Transient Reverse Bias Reliability of β-Ga2O3 Based Vertical Schottky Barrier Diodes”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  23. Rasik Rashid Malik, Vipin Joshi, Rajarshi R. Chaudhuri, Mehak A. Mir, Zubear Khan, Avinas N Shaji, Madhura Bhattacharya, Anup T. Vitthal, and Mayank Shrivastava, “Signatures of Positive Gate Over-Drive Induced Hole Trap Generation and its Impact on p-GaN Gate Stack Instability in AlGaN/GaN HEMTs”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  24. Vipin Joshi, Sayak Dutta Gupta, Rajarshi Roy Chaudhuri, and Mayank Shrivastava, “Unique Dependence of the Breakdown Behavior of Normally-OFF Cascode AlGaN/GaN HEMTs on Carrier Transport Through the Carbon Doped GaN Buffer”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  25. Rupali Verma, Utpreksh Patbhaje, Anand Kumar Rai, Jeevesh Kumar, and Mayank Shrivastava, “OFF State Reliability Challenges of Monolayer WS2 FET Photodetector: Impact on the Dark and Photo-illuminated state”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  26. Jeevesh Kumar, Hemanjaneyulu Kuruva, and Mayank Shrivastava, “Atomic-level Insight and Quantum Chemistry of Ambient Reliability Issues of the TMDs Devices”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  27. Anand Kumar Rai and Mayank Shrivastava, “Circuit Reliability of MoS2 Channel Based 2D Transistors”, to appear in the proceedings of 61st IEEE International Reliability Physics Symposium, IEEE IRPS 2023, March 26-30, 2023 – Monterey, California
  28. Aakanksha Mishra, Sampath Kumar Boeila, Avinash Kumar Singh, Shubhank Gupta, M. Monish Murali, Amit Kumar Singh, Ankur Gupta and Mayank Shrivastava, “Inverted SOA and Transient Non-Linearity of LDMOS Devices With RESURF-Implant”, to appear in the proceedings of 6th IEEE ICEE, Dec 11th – 14th.
  29. Rajat Sinha, Sanjiv Sambandan and Mayank Shrivastava, “On the ESD Behavior of Hydrogenated Amorphous Silicon Based High- Voltage TFTs”, to appear in the proceedings of 6th IEEE ICEE, Dec 11th – 14th.
  30. Harsha B Variar, Ajay Singh, Ankit Soni and Mayank Shrivastava, “Exploring the Feasibility of AlN/GaN HEMTs for THz Applications Using a Novel Device-Circuit Co-Design Approach”, to appear in the proceedings of 6th IEEE ICEE, Dec 11th – 14th.
  31. Harsha B Variar, Jhnanesh Somayaji and Mayank Shrivastava, “Physical Insights Into the ESD Behavior of Field Plated UHV LDMOS Devices”, to appear in the proceedings of 6th IEEE ICEE, Dec 11th – 14th.
  32. Satendra Kumar Gautam, Jatin, M. Monish Murali and Mayank Shrivastava, “The Physical Insight Into Holding Voltage Engineering of SCR for ESD Protection”, to appear in the proceedings of 6th IEEE ICEE, Dec 11th – 14th.
  33. Jeevesh Kumar and Mayank Shrivastava, “Are Argon and Nitrogen Gases Really Inert to Graphene Devices”, to appear in the Proceedings of the 80th IEEE Device Research Conference (DRC), Columbus, Ohio, June 26-29, 2022
  34. Rajat Sinha, Sanjiv Sambandan and Mayank Shrivastava, “On the ESD Behavior of a- Si: H Based Diode-Connected Thin- Film Transistor”, to appear in the proceedings of 6th IEEE ICEE, Dec 11th – 14th.
  35. Harsha B Variar, Kranthi Nagothu, Hemanjaneyulu Kuruva and Mayank Shrivastava, “ESD Behavior of Fin Based Tunnel FETs”, to appear in the proceedings of 6th IEEE ICEE, Dec 11th – 14th.
  36. Harsha B Variar, Jhnanesh Somayaji and Mayank Shrivastava, “Performance and Reliability Co-Design of Ultra High Voltage LDMOS Devices”, to appear in the proceedings of 6th IEEE ICEE, Dec 11th – 14th.
  37. Monish Murali, Nagothu Karmel Kranthi, Gianluca Boselli and Mayank Shrivastava, “Effect of Source & Drain Side Abutting on the Low Current Filamentation in LDMOS-SCR Devices”, Proceedings of 60th IEEE International Reliability Physics Symposium (IRPS), Dallas, USA, March 27th-31st, 2022.
  38. Jatin, M. Monish Murali, Satendra Kumar Gautam and Mayank Shrivastava, “Performance and Reliability Co-Design of HV Devices in Vertically Stacked Nanosheet Technology”, to appear in the proceedings of 6th IEEE ICEE, Dec 11th – 14th.
  39. Harsha B Variar, Ajay Singh, Jhnanesh Somayaji and Mayank Shrivastava, “Device-Circuit Co-Design and ESD/HCI Reliability Aware Design of Field Plated RF LDMOS Devices”, to appear in the proceedings of 6th IEEE ICEE, Dec 11th – 14th.
  40. Jeevesh Kumar, Utpreksh Patbhaje and Mayank Shrivastava, “Unveiling Additional Ambient Degradation Issues of Phosphorene FETs Under Laser Exposure and Positive Gate Bias”, to appear in the proceedings of 6th IEEE ICEE, Dec 11th – 14th.
  41. Monish Murali and Mayank Shrivastava, “A Novel High Voltage Drain Extended FinFET SCR for SoC Applications”, Proceedings of 59th IEEE International Reliability Physics Symposium (IRPS), USA, March 21-25, 2021. DOI: 10.1109/IRPS46558.2021.9405194
  42. Monish Murali and Mayank Shrivastava, “Peculiar Current Instabilities & Failure Mechanism in Vertically Stacked Nanosheet ggN-FET”, Proceedings of 59th IEEE International Reliability Physics Symposium (IRPS), USA, March 21-25, 2021. DOI: 10.1109/IRPS46558.2021.9405147
  43. Jhnanesh Somayaji B, Monishmurali, Ajay Singh, Kranthi N.K. and Mayank Shrivastava, “3D TCAD studies of Snapback Driven Failure in Punchthrough TVS Diodes under System Level ESD Stress Conditions”, Proceedings of 42nd EOSESD Symposium, September 2020, Sep. 13th – Sep. 18th, USA.
  44. Nagothu Karmel Kranthi, James Di Sarro, Rajkumar Sankaralingam, Gianluca Boselli and Mayank Shrivastava, “Insights into the System Level IEC ESD Failure in High Voltage DeNMOS-SCR for Automotive Applications”, Proceedings of 42nd EOSESD Symposium, September 2020, Sep. 13th – Sep. 18th, USA
  45. Jeevesh Kumar, Ansh, Hemanjaneyulu Kuruva and Mayank Shrivastava, “Defect Assisted Metal-TMDs Interface Engineering: A First Principle Insight”, 78th Device Research Conference (DRC), June 21st – 24th, 2020, USA. DOI: 10.1109/DRC50226.2020.9135158
  46. Rajat Sinha, Prasenjit Bhattacharya, Sanjiv Sambandan and Mayank Shrivastava, “Threshold voltage shift in a-Si:H Thin film transistors under ESD stress”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9128355
  47. Nagothu Karmel Kranthi, B. Sampath Kumar, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Design Insights to Address Low Current ESD Failure and Power Scalability Issues in High Voltage LDMOS-SCR Devices”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9129624
  48. Nagothu Karmel Kranthi, B. Sampath Kumar, Chirag Garg, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “How to Achieve Moving Current Filament in High Voltage LDMOS Devices: Physical Insights & Design Guidelines for Self-Protected Concepts”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9128332
  49. Monish Murali M, Milova Paul and Mayank Shrivastava, “Improved Turn-on Uniformity & Failure Current Density by n- & p-Tap Engineering in Fin Based SCRs”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9129356
  50. Ansh, Gaurav Sheoran, Jeevesh Kumar and Mayank Shrivastava, “First Insights into Electro-Thermal Stress Driven Time-Dependent Permanent Degradation & Failure of CVD Monolayer MoS2 Channel”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9129173
  51. Jeevesh Kumar, Asha Yadav, Anant Kumar Singh, Andrew Naclerio, Dmitri Zakharov, Piran Kidambi and Mayank Shrivastava, “Physical Insights into Phosphorene Transistor Degradation Under Exposure to Atmospheric Conditions and Electrical Stress”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9129123
  52. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri, Anant kr. Singh, Sirsha Guha and Mayank Shrivastava, “On the Root Cause of Dynamic ON Resistance Behavior in AlGaN/GaN HEMTs”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9128226
  53. Aakanksha Mishra, B. Sampath Kumar, Jhnanesh Somayaji, Mayank Shrivastava and Ankur Gupta, “Impact of Space Charge Modulation on Superjunction-LDMOS”, IEEE VLSI-TSA, Taiwan, April 2020. DOI: 10.1109/VLSI-TSA48913.2020.9203659
  54. Rajarshi Roy Chaudhuri, Sayak Dutta Gupta, Vipin Joshi and Mayank Shrivastava, “Interaction of Hot Electrons with Carbon Doped GaN Buffer in AlGaN/GaN HEMTs: Correlation with Lateral Electric Field and Device Failure”, Proceedings of 32nd IEEE International Symposium on Power Semiconductor Devices and ICs, Vienna, Austria, May 17-21, 2020. DOI: 10.1109/ISPSD46842.2020.9170160
  55. Jeevesh Kumar, Adil Meersha, Ansh and Mayank Shrivastava, “A First Principle Insight into Defect Assisted Contact Engineering at the Metal-Graphene and Metal-Phosphorene Interfaces”, 24th IEEE SISPAD, Italy, September 2019. DOI: 10.1109/SISPAD.2019.8870396
  56. Nagothu Karmel Kranthi, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Performance and Reliability Co-Design of LDMOS-SCR for Self-Protected High Voltage Applications on-Chip”, 31st IEEE Intl. Symposium on Power Semiconductor Devices & ICs, May 19-23, 2019. DOI: 10.1109/ISPSD.2019.8757641
  57. Nagothu Karmel Kranthi, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Current Filament Dynamics Under ESD Stress in High Voltage (Bidirectional) SCRs and Its Implications on Power Law Behavior”, 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019. DOI: 10.1109/IRPS.2019.8720484
  58. Abhishek Mishra, Adil Meersha, N. K. Kranthi, Kruti Trivedi, Harsha B. Variar, Veena Bellamkonda, Srinivasan Raghavan and Mayank Shrivastava, “First Demonstration and Physical Insights into Time-dependent Breakdown of Graphene Channel and Interconnects”, 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019. DOI: 10.1109/IRPS.2019.8720452
  59. Sayak Dutta Gupta, Vipin Joshi, Srinivasan Raghavan and Mayank Shrivastava, “UV-Assisted Probing of Deep-Level Interface Traps in GaN MISHEMTS and Its Role In Threshold Voltage & Gate Leakage Instabilities”, 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019. DOI: 10.1109/IRPS.2019.8720595
  60. Nagothu Karmel Kranthi, B. Sampath Kumar, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Physical Insights into the Low Current ESD Failure of LDMOS-SCR and Its Implication on Power Scalability”, 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019. DOI: 10.1109/IRPS.2019.8720580
  61. Bhawani Shankar, Ankit Soni, Sayak Dutta Gupta, Swati Shikha, Sandeep Singh, Srinivasan Raghavan and Mayank Shrivastava, “Time Dependent Early Breakdown of AlGaN/GaN Epi Stacks and Shift in SOA Boundary of HEMTs Under Fast Cyclic Transient Stress”, 64th IEEE International Electron Device Meeting (IEDM)– 2018, CA, USA, DOI: 10.1109/IEDM.2018.8614690
  62. Kuruva Hemanjaneyulu, Mamta Khaneja, Adil Meersha, Harsha B Variar and Mayank Shrivastava, “Comprehensive Computational Modelling Approach for Graphene FETs”, 4th IEEE ICEE, 2018. DOI: 10.1109/ICEE44586.2018.8937909
  63. B Sampath Kumar, Milova Paul, Harald Gossner and Mayank Shrivastava, “Physical Insights into the ESD Behavior of Drain extended FinFETs”, to appear in 40th EOSESD Symposium, Sep. 23rd to 28th 2018, Reno, NV, USA DOI: 10.23919/EOS/ESD.2018.8509695
  64. Bhawani Shankar, Rahul Singh, Rudrarup Sengupta, Heena Khand, Ankit Soni, Sayak D. Gupta, Srinivasan Raghavan and Mayank Shrivastava, “Trap Assisted Stress Induced ESD Reliability of GaN Schottky Diodes”, to appear in 40th EOSESD Symposium, Sep. 23rd to 28th 2018, Reno, NV, USA DOI: 10.23919/EOS/ESD.2018.8509745
  65. Bhawani Shankar, A. Soni, S. D. Gupta and Mayank Shrivastava, “Safe Operating Area (SOA) Reliability of Polarization Super Junction (PSJ) GaN FETs”, 56th IEEE International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353595
  66. Milova Paul, B. Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Contact and Junction Engineering in Bulk FinFET Technology for Improved ESD/Latch-up Performance with Design Trade-offs and Its Implications on Hot Carrier Reliability”, 56th IEEE International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353573
  67. Bhawani Shankar, Ankit Soni, Sayak Dutta Gupta, R. Sengupta, H. Khand, N. Mohan, Srinivasan Raghavan and Mayank Shrivastava, “On the Trap Assisted Stress Induced Safe Operating Area Limits of AlGaN/GaN HEMTs”, 56th IEEE International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353596
  68. N. K. Kranthi, Abhishek Mishra, Adil Meersha, Harsha B. Variar and Mayank Shrivastava, “Defect-Assisted Safe Operating Area Limits and High Current Failure in Graphene FETs”, 56th IEEE International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353571
  69. Rajat Sinha, Prasenjit Bhattacharya, Sanjiv Sambandan and Mayank Shrivastava, “On the ESD Behavior of a-Si:H based Thin-Film Transistors: Physical Insights, Design and Technological Implications”, 56th IEEE  International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353572
  70. Sampath Kumar B, Milova Paul, Harald Gossner and Mayank Shrivastava, “Performance and Reliability Insights of Drain Extended FinFET Devices for High Voltage SoC Applications”, 30th Int’l Symposium on Power Semiconductor Devices and ICs (ISPSD), Chicago, USA, May 13-17, 2018. DOI: 10.1109/ISPSD.2018.8393605
  71. Karmel Kranthi Nagothu, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “On the ESD Reliability issues in Carbon electronics: Graphene and Carbon Nano Tubes”, 31st International Conference on VLSI Design (VLSID), Jan 2018. DOI: 10.1109/VLSID.2018.117
  72. Vipin Joshi, Bhawani Shankar, Shree Prakash Tiwari and Mayank Shrivastava, “Dependence of Avalanche Breakdown on Surface & Buffer Traps in AlGaN/GaN HEMTs”, 22nd IEEE SISPAD, Japan, September 7-9, 2017 DOI: 10.23919/SISPAD.2017.8085276
  73. B. Sampath Kumar, Milova Paul and Mayank Shrivastava, “On the Design Challenges of Drain Extended FinFETs for Advance SoC Integration”, 22nd IEEE SISPAD, Japan, September 7-9, 2017 DOI: 10.23919/SISPAD.2017.8085296
  74. Adil Meersha, Harsha B Variar, Krishna Bharadwaj, Abhishek Mishra, Srinivasan Raghavan, Navakanta Bhat and Mayank Shrivastava, “Record Low Metal – (CVD) Graphene Contact Resistance Using Atomic Orbital Overlap Engineering”, Proceedings of IEEE International Electron Device Meeting, Dec. 5th – Dec. 7th, San Francisco, CA, USA, 2016 DOI: 10.1109/IEDM.2016.7838352
  75. N. K. Kranthi, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “ESD Behavior of Large Area CVD Graphene RF Transistors: Physical Insights and Technology Implications”, Proceedings of 55th IEEE International Reliability Physics Symposium (IRPS), USA, April 4th – April 6th, 2017  DOI: 10.1109/IRPS.2017.7936298
  76. Bhawani Shankar, Ankit Soni, Manikant Singh, Rohith Soman, Hareesh Chandrasekar , Nagaboopathy Mohan, Neha Mohta, Nayana Ramesh, Shreesha Prabhu, Abhay Kulkarni, Digbijoy Nath, R. Muralidharan, K. N. Bhat, Srinivasan Raghavan, Navakant Bhat and Mayank Shrivastava, “Trap Assisted Avalanche Instability and Safe Operating Area Concerns in AlGaN/GaN HEMTs”, Proceedings of 55th IEEE International Reliability Physics Symposium (IRPS), USA, April 4th – April 6th, 2017 DOI: 10.1109/IRPS.2017.7936414
  77. Milova Paul, B. Sampath Kumar, Christian Russ, Harald Gossner and Mayank Shrivastava, “FinFET SCR: Design Challenges and Novel Fin SCR Approaches for On-Chip ESD Protection”, Proceedings of 39th EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA DOI: 10.23919/EOSESD.2017.8073437
  78. Bhawani Shankar, Rudrarup Sengupta, Sayak Dutta Gupta, Ankit Soni, Nagaboopathy Mohan, Navakant Bhat, Srinivasan Raghavan and Mayank Shrivastava, “On the ESD Behavior of AlGaN/GaN Schottky Diodes and Trap Assisted Failure Mechanism”, Proceedings of 39th EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA DOI: 10.23919/EOSESD.2017.8073423
  79. Rajat Sinha, N.K. Kranthi, Sanjiv Sambandan and Mayank Shrivastava, “On the ESD Behavior of Pentacene Channel Organic Thin Film Transistor”, Proceedings of 39th EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA DOI: 10.23919/EOSESD.2017.8073426
  80. Abhishek Mishra and Mayank Shrivastava, “Unique Current Conduction Mechanism through Multi Wall CNT Interconnects under ESD Conditions”, Proceedings of 38th EOSESD Symposium, Anaheim, CA, USA, 11th – 14th September, 2016 DOI: 10.1109/EOSESD.2016.7592528
  81. Abhishek Mishra and Mayank Shrivastava, “New Insights on the ESD Behavior and Failure Mechanism of Multi Wall CNTs”, Proceedings of 54th IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, USA, 17th – 19th April, 2016 DOI: 10.1109/IRPS.2016.7574609
  82. Bhawani Shankar and Mayank Shrivastava, “Unique ESD Behavior and Failure Modes of AlGaN/GaN HEMTs”, Proceedings of 54th IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, USA, 17th – 19th April, 2016 DOI: 10.1109/IRPS.2016.7574608
  83. Milova Paul, Christian Russ, B Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete?”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017 (Received outstanding research paper award) DOI: 10.1109/VLSID.2017.32
  84. Bhawani Shankar and Mayank Shrivastava, “ESD Behavior of AlGaN/GaN HEMT on Si: Physical Insights, Design Aspects, Cumulative Degradation and Failure Analysis”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017 DOI: 10.1109/VLSID.2017.57
  85. Adil Meersha, Sathyajit B and Mayank Shrivastava, “A Systematic Study on the Hysteresis Behavior and Reliability of MoS2 FET”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017 DOI: 10.1109/VLSID.2017.67
  86. Peeyusha S. Swain, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “Device-Circuit Co-design for High Performance Level Shifter by Limiting Quasi-saturation Effects in Advanced DeMOS Transistors”, IEEE INEC, 9th – 11th, May, 2016, China DOI: 10.1109/INEC.2016.7589264
  87. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology mounted in BGA Package”, Proceedings of IEEE VLSI Design Conference, Jan. 2016 DOI: 10.1109/VLSID.2016.30
  88. Ketankumar Tailor, Mayank Shrivastava, Harald Gossner, Maryam Baghini, Ramgopal Rao, “On the Breakdown Physics of Trench-Gate Drain Extended NMOS”, Proceedings of IEEE Electron Devices and Solid-State Circuits Conference, June 2015, Singapore. DOI: 10.1109/EDSSC.2015.7285240
  89. Ketankumar Tailor, Mayank Shrivastava, Harald Gossner, Maryam Baghini, Ramgopal Rao, “Comparison of Breakdown Characteristics of DeNMOS Devices with Various Drain Structures”, Proceedings of IEEE Electron Devices and Solid-State Circuits Conference, June 2015, Singapore. DOI: 10.1109/EDSSC.2015.7285222
  90. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Drain Extended MOS Device Design for Integrated RF PA in 28nm CMOS with Excellent FoM and ESD Robustness”, Proceeding of IEEE International Electron Device Meeting (IEDM) Dec. 2014, San Francisco, CA, USA. DOI: 10.1109/IEDM.2014.7046974
  91. Mayank Shrivastava and Harald Gossner, “ESD Behavior of Metallic Carbon Nanotubes”, Proceedings of 36th EOSESD Symposium, 7th – 12th Sep. 2014, Tucson, Arizona, USA. INSPEC Accession Number: 14789864
  92. Mayank Shrivastava, Christian Russ, Harald Gossner, S. Bychikhin, D. Pogany and E. Gornik, “ESD Robust DeMOS Devices in Advanced CMOS Technologies”, Proceedings of EOSESD symposium, 11th – 15th Sep. 2011, Anaheim, California, USA. NSPEC Accession Number: 12316388
  93. Junjun Li, Rahul Mishra, Mayank Shrivastava, Yang Yang, Robert Gauthier, Christian Russ, “Technology Scaling Effects of Silicide-blocked PMOSFET Devices under ESD like conditions in Advanced Nanometer Node Bulk CMOS Technologies”, Proceedings of EOSESD Symposium, 11-15 Sep. 2011, Anaheim, California, USA INSPEC Accession Number: 12316385.
  94. Mayank Shrivastava, Manish Agrawal, Jasmin Aghassi, Harald Gossner, Wolfgang Molzer, Thomas Schulz, V. Ramgopal Rao, “On the thermal failure in nanoscale devices: Insight towards Heat Transport and Design Guidelines for Robust Thermal Management & EOS/ESD Reliability”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), 10-14 April, 2011, Monterey, CA, USA. DOI: 10.1109/IRPS.2011.5784498
  95. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini and V. Ramgopal Rao, “On the Transient Behavior of Various Drain Extended MOS Devices under the ESD stress conditions”, Proceedings of 7th International SoC Design Conference (ISOCC 2010), November 22-23, 2010, Songdo Convensia, Incheon, Korea (Invited) DOI: 10.1109/SOCDC.2010.5682922
  96. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini and V. Ramgopal Rao, “3D TCAD based approach for the Evaluation of Nanoscale Devices during ESD Failure”, Proceedings of 7th International SoC Design Conference (ISOCC 2010), November 22-23, 2010, Songdo Convensia, Incheon, Korea (Invited) DOI: 10.1109/SOCDC.2010.5682919
  97. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “On the failure mechanism and current instabilities in RESURF type DeNMOS device under ESD conditions”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), May 2nd – 6th, 2010, Anaheim, California, USA. DOI: 10.1109/IRPS.2010.5488723
  98. Mayank Shrivastava, S. Bychikhin, D. Pogany, Jens Schneider, M. Shojaei Baghini, Harald Gossner, Erich Gornik, V. Ramgopal Rao, “On the differences between 3D filamentation and failure of n & p type drain extended MOS devices under ESD condition”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), May 2nd – 6th, 2010, Anaheim, California, USA. DOI: 10.1109/IRPS.2010.5488785
  99. Mayank Shrivastava, Bhaskar Verma, M. Shojaei Baghini, Christian Russ, Dinesh K. Sharma, Harald Gossner, V. Ramgopal Rao, “Benchmarking the Device Performance at sub 22 nm node Technologies using an SoC Framework”, Proceedings of IEEE International Electron Device Meeting (IEDM), 7th -9th Dec, 2009, Baltimore, USA. DOI: 10.1109/IEDM.2009.5424311
  100. Mayank Shrivastava, S. Bychikhin, D. Pogany, Jens Schneider, M. Shojaei Baghini, Harald Gossner, Erich Gornik, V. Ramgopal Rao, “Filament Study of STI type Drain extended NMOS device using Transient Interferometric Mapping”, Proceedings of IEEE International Electron Device Meeting (IEDM), 7th -9th Dec, 2009, Baltimore, USA. DOI: 10.1109/IEDM.2009.5424337
  101. Mayank Shrivastava, Jens Schneider, Ruchil Jain, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “IGBT plugged in SCR device for ESD protection in advanced CMOS technology”, Proceedings of EOS/ESD symposium, August 30th – September 4th, 2009, Anaheim, CA, USA. INSPEC Accession Number: 10980103
  102. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “Highly resistive body STI: n-DEMOS: An optimized DEMOS device to achieve moving current filaments for robust ESD protection”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), April 26th – 30th, 2009, Montreal, Quebec, Canada. DOI: 10.1109/IRPS.2009.5173344
  103. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “A New Physical Insight and 3D Device Modeling of STI Type DENMOS Device Failure under ESD Conditions”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), April 26th – 30th, 2009, Montreal, Quebec, Canada. DOI: 10.1109/IRPS.2009.5173327

Other Peer Reviewed International Conferences

  1. Purbasha Ray, Rupali Verma, Mayank Shrivastava, Prasana K. Sahoo “2D MoSe2-WSe2 Lateral Heterostructure Based Emerging Electronics” accepted for poster presentation at the International Conference on Functional Materials (ICFM), 2024
  2. Biswajeet Nayak, Rupali Verma, Mayank Srivastava, and Prasana Kumar Sahoo “Controlled Growth of large area 2D Transition Metal Dichalcogenides and Lateral Heterostructures, and their Electrical Characteristics” accepted for poster presentation at the International Conference on Functional Materials (ICFM), 2024
  3. Biswajeet Nayak, Rupali Verma, Purbasha Ray, Suman Kumar Chakraborty, Praveen Kumar, Mayank Shrivastava, Prasana K. Sahoo “Growth of 2D Lateral Heterostructures via controlled Edged-Epitaxy and their Device Characteristics” accepted for poster presentation at Recent Progress in Graphene and 2D Materials Research (RPGR), 2023
  4. Purbasha Ray, Rupali Verma, Biswajeet Nayak, Suman Kumar Chakraborty, Praveen Kumar, Mayank Shrivastava, Prasana K. Sahoo “Direct Fabrication of 2D Lateral P-N Junction Diode via CVD” accepted for poster presentation at the International Workshop on the Physics of Semiconductor Devices (IWPSD), 2023
  5. Anand Kumar Rai and Mayank Shrivastava, “Partial and Complete Edge Contacts-Based Enhancement in Electron and Hole Current of MoS2 FETs”, to be presented at Graphene Week 2023, 4-8 September 2023 in Gothenburg, Sweden
  6. Anand Kumar Rai and Mayank Shrivastava, “Plasma and Pulse Stress Combined Effect for Performance Boosting of Exfoliated and CVD-Grown MoS2 FETs”, Graphene Week 2023, 4-8 September 2023 in Gothenburg, Sweden
  7. Utpreksh Patbhaje and Mayank Shrivastava, “Charge Neutrality Point Alignment Strategy using Terminal Voltages in MoSe2 FETs”, to be presented at Graphene Week 2023, 4-8 September 2023 in Gothenburg, Sweden
  8. Utpreksh Patbhaje and Mayank Shrivastava, “Inconsistencies in Current Trends in MoSe2 FETs Under Long Term Operation”, to be presented at Graphene Week 2023, 4-8 September 2023 in Gothenburg, Sweden
  9. Vipin Joshi, Sayak Dutta Gupta, Rajarshi Roy Chaudhuri, and Mayank Shrivastava, “Unique C-doped GaN Buffer Transport Dependence of Breakdown Voltage in Normally-OFF Cascode HEMTs,” 2022 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2022.
  10. S. K. Gautam, Jatin, M. Monishmurali, and Mayank Shrivastava, “The Physical Insight into Holding Voltage Engineering of SCR for ESD Protection,” 2022 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2022.
  11. Jatin, S. K. Gautam, M. Monishmurali, and Mayank Shrivastava, “Performance and Reliability Co-Design of HV devices in Vertically Stacked Nanosheet Technology,” 2022 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2022.
  12. Utpreksh Patbhaje, Rupali Verma, and Mayank Shrivastava, “Unique Reliability Concern on Intrinsic MoSe2 FET Channel”, Graphene Week 2022, Munich, Germany, September 5-9, 2022
  13. Jeevesh Kumar, Utpreksh Patbhaje, and Mayank Shrivastava, “Atomic-level investigation to resolve performance and reliability bottlenecks of the 2D material devices for the electronic application”, Graphene Week 2022, Munich, Germany, September 5-9, 2022
  14. Rupali Verma, Utpreksh Patbhaje, and Mayank Shrivastava, “Effect of in-plane electric field on the excitonic photoluminescence quenching and photocurrent generation in monolayer WS2”, Graphene Week 2022, Munich, Germany, September 5-9, 2022
  15. Anand Kumar Rai and Mayank Shrivastava, “Plasma and Pulse Stress Combined Flawless Effect for Performance Boosting of MoS2 FETs”, Graphene Week 2022, Munich, Germany, September 5-9, 2022
  16. Rajarshi Roy Chaudhuri, Vipin Joshi, Sayak Dutta Gupta, and Mayank Shrivastava, “Hot Electron Interaction with C-doped GaN buffer and Resultant Gate Leakage Degradation in AlGaN/GaN HEMTs,” GaN Marathon 2022, Venice, Italy, June 20-22, 2022
  17. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri, and Mayank Shrivastava, “Physics-Based Approach for Mitigation of Dynamic RON in AlGaN/GaN HEMTs with C-doped buffer,” GaN Marathon 2022, Venice, Italy, June 20-22, 2022
  18. Mayank Shrivastava, “Reliable Enhancement-Mode AlGaN/GaN HEMTs by p-type AlTiO Based Gate Stack Engineering,” GaN Marathon 2022, Venice, Italy, June 20-22, 2022
  19. Rajarshi Roy Chaudhuri, Vipin Joshi, Sayak Dutta Gupta, and Mayank Shrivastava, “Experimental Observations of Hot Electron Interaction with Traps in C-doped GaN buffer in AlGaN/GaN HEMTs: Investigating the Role of Lateral Electric Field”, GaN Marathon 2020, Padua, Italy, April 2020
  20. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri, and Mayank Shrivastava, ” Physical insights into Dynamic RON in AlGaN/GaN HEMTs with carbon-doped buffer”, GaN Marathon 2020, Padua, Italy, April 2020
  21. Gaurav Sheoran, Jeevesh Kumar, Ansh, Srinivasan Raghavan and Mayank Shrivastava, “Universal approach to achieve enhanced ambipolar behaviour in all TMDs and CVD monolayer MoS2 based Field Effect Transistors (FETs)”, Graphene 2019, Rome, Italy, June 2019.
  22. Ansh, Jeevesh Kumar, Ravi K Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Chalcogen assisted contact engineering: towards CMOS circuit integration of WSe2 FETs”, Graphene 2019, Rome, Italy, June 2019.
  23. Harsha Variar, Jeevesh Kumar, Ansh, Srinivasan Raghavan and Mayank Shrivastava, “Overall performance improvement of Transition Metal Dichalcogenides (TMDs) based Field-Effect Transistors (FETs) via Chalcogen assisted channel and contact engineering”, Graphene 2019, Rome, Italy, June 2019.
  24. Jeevesh Kumar, Ansh, Adil Meersha and Mayank Shrivastava, “A deep Insight into Defect Engineering at the Metal-Graphene and Metal-Phosphorene Interfaces”, Graphene 2019, Rome, Italy, June 2019.
  25. Hemanjaneyulu Kuruva, Jeevesh Kumar and Mayank Shrivastava, “Improving the efficiency of MoS2 based FETs through Potassium Iodide doping”, Graphene 2019, Rome, Italy, June 2019.
  26. Ansh, Jeevesh Kumar, Gaurav Sheoran, Ravi K Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Chalcogen assisted contact engineering: a universal approach to realize enhanced hole injection across CVD TMD monolayer – metal interfaces”, Graphene Week 2019, Finland, September 2019.
  27. Ansh, Jeevesh Kumar, Ravi K Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Chalcogen assisted contact engineering led unique MIGS and DIGS at WSe2-metal interface enabling CMOS circuit integration of WSe2 transistors”, Graphene Week 2019, Finland, September 2019.
  28. Jeevesh Kumar, Ansh, Adil Meersha and Mayank Shrivastava, “A First Principle Insight into Defect Engineering at the Metal-Graphene and Metal-Phosphorene Interfaces”, to appear in Graphene Week 2019, Finland, September 2019.
  29. Jeevesh Kumar, Ansh and Mayank Shrivastava, “A First Principle Insight into Defect Assisted Band Gap Creation in Graphene”, to appear in Graphene Week 2019, Finland, September 2019.
  30. Abhishek Mishra, Adil Meersha, V Bellamkonda, G Sheoran, A Rao, Srinivasan Raghavan, Mayank Shrivastava, Investigation of Time-evolution of Electro-thermal Transport through Graphene-based Transistors and its Impact on the Device Reliability, to appear in Graphene Week 2019, Finland, September 2019.
  31. B. Shankar, A. Soni, S. Dutta Gupta, R. Sengupta, H. Khand, N. Mohan, S. Raghavan, N. Bhat, and Mayank Shrivastava, “Design and Reliability of GaN Power HEMT Technology”, AiMES 2018 Meeting (September 30 – October 4, 2018) (Invited) http://ma.ecsdl.org/content/MA2018-02/16/713.short
  32. Mayank Shrivastava, Christian Russ, Harald Gossner, “On the Impact of ESD Implant and Filament Spreading in Drain extended NMOS devices”, International ESD Workshop, May 2011, Lake Tahoe, CA, USA.
  33. A. B. Sachid, Mayank Shrivastava, R. A. Thakkar, M. Shojaei Baghini, D. K. Sharma, M. B. Patil, V. Ramgopal Rao, “Technology-Aware Design (TAD) for Sub-45nm CMOS Technologies”, Intel Asia Academic Forum 2008, Oct. 20th – Oct. 22nd 2008, Taipei, Taiwan. (Received the best research paper award).
  34. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Reliability aware I/O design for sub 45nm node CMOS technology”, IWPSD-2009, 15th -19th Dec, 2009 (Invited).