Prof. Mayank Shrivastava
Associate Professor
Department of Electronic Systems Engineering
Indian Institute of Science Bangalore, 560012
Co-Founder, AGNIT Semiconductors Pvt. Ltd.
Investigator, Gallium Nitride EcoSystem Enabling Center (GaN Fab)
E-mail: mayank@iisc.ac.in
Web: http://mayank.dese.iisc.ac.in/
Contact: +91-80-2293-2732 / +91 9686340309

Bio and Key Contributions

Biography:Prof. Mayank Shrivastava is a faculty member at the Indian Institute of Science, Bangalore, and co-founder of AGNIT Semiconductors Pvt. Ltd. He is also an editor of the IEEE Transactions on Electron Devices. For his PhD work, he received Excellence in Research award and the Industrial Impact award from IIT Bombay in 2010. He is among the first recipients of the Indian section of the American TR35 award (2010) and a recipient of IEEE EDS Early Career Award (2015). He is the recipient of prestigious DST Swarnjayanti Fellowship (2021), Abdul Kalam Technology Innovation National Fellowship from INAE-SERB (2021) and VASVIK award (2021). He has received several other national awards and honours of high repute, like the National Academy of Sciences, India, (NASI) Young Scientist Platinum Jubilee Award – 2018; Indian National Academy of Science (INSA) Young Scientist Award – 2018; Indian National Academy of Engineering (INAE) Innovator Entrepreneur Award 2018 (Special commendation); Indian National Academy of Engineering (INAE) Young Engineer Award – 2017; INAE Young Associate (since 2017); Indian Academy of Sciences (IASc), Young Associate, 2018 – 2023; Ministry of Electronics & Information Technology (MeitY), Young Faculty Fellowship. Besides, he received best paper awards from several international conferences like Intel Corporation Asia academic forum, VLSI design Conference and EOSESD Symposium. Prof Shrivastava broadly works on applications of emerging materials like Gallium Nitride (GaN), atomically thin two-dimensional materials like Graphene and TMDCs, in electronic and electro-optic devices working closer to its fundamental limits (like the ability to handle extreme powers, ability to work at THz like ultra-high frequencies, or ability to compute information in unconventional ways). Currently, his group is developing few-atom thick devices & circuits, GaN-based ultra-high-power devices with high reliability, and devices/circuits for operation at THz frequencies. Besides, his group also works on developing novel ESD and High Voltage devices in advanced CMOS nodes. He had held visiting positions in Infineon Technologies, Munich, Germany, from April 2008 to October 2008 and again in May 2010 to July 2010. He worked for Infineon Technologies, East Fishkill, NY, USA; IBM Microelectronics, Burlington, VT, USA; Intel Mobile Communications, Hopewell Junction, NY, USA; Intel Corp, Mobile and Communications Group, Munich, Germany between 2010 and 2013. He joined the Indian Institute of Science as a faculty member in the year 2013. Prof Shrivastava’s work has resulted in over 180 peer-reviewed publications and 50 patents. Most of these patents are either licensed by semiconductor companies or are in use in their products.

Key Contributions : Prof. Shrivastava’s group works on (i) probing the fundamental challenges or roadblocks in enabling the next generation nanoelectronics and power semiconductor device technologies and (ii) translating the new science discovered into better / industrially relevant semiconductor technologies.

On the nanoelectronics front, in the past five years, his group has primarily focused on graphene and other 2D materials, such as transition metal dichalcogenide (TMDs), based technologies. Despite the remarkable potential of these next-generation platforms, these technologies were plagued by several fundamental showstoppers, such as (i) how to interface/connect these 2-dimensional materials with a 3-dimensional world with interface resistance close to quantum limits, (ii) how to develop reliable transistors with performance close to its theoretical limits, and (iii) how to enable a p-channel transistor without which industries couldn’t build CMOS circuits or 2D chips. Prof. Shrivastava’s works probed the quantum chemistry of 3D (metal) – 2D (graphene/TMDs) interfaces, which enabled him to develop novel methods to engineer the contacts (metal-2D interface) for all key 2D channels while achieving record low contact resistance crossing the quantum limit predicted earlier. Besides, his group probed the root cause behind several other performance and reliability showstoppers, such as current-voltage hysteresis behavior, lower mobilities, implications of point defects, defect annealing, time-dependent breakdown, e-field assisted material reconfiguration, etc. and developed physical insights into these phenomena using detailed experiments and first principal methods. These insights enabled the nominee to devise methods to address performance and reliability showstoppers in 2D semiconductor technologies. It resulted in record high-performance transistors using all the key 2D channels (such as graphene, MoS2, WS2, MoSe2 and WSe2) with engineered contacts. Finally, his group could also address the quest for enabling p-channel conduction, which is essential for developing p-type (or complimentary) transistors. A missing p-channel transistor has been the showstopper for semiconductor industries to demonstrate CMOS chips using 2D semiconductors. The experimental and computational probes enabled Prof. Shrivastava’s group to selectively engineer mid-gap states to develop p-channel and n-channel transistors in the same chip – enabling the CMOS operation for the first time with record-high performance. These findings and technology modules also enabled his group to demonstrate better synaptic devices using these 2D materials for on-chip neuromorphic applications.

On the power semiconductor device front, in the past five years, Prof. Shrivastava’s group has primarily worked on Gallium Nitride (GaN) HEMTs and Si LDMOS devices with a quest to address the performance and reliability showstoppers to push their operations closer to theoretical limits. As GaN HEMTs are normally-ON by default, the fundamental question was how to enable a normally-OFF HEMT, which is a must for power electronics applications. Besides, GaN HEMTs suffered several reliability challenges, primarily attributed to lack of fundamental insights into phenomena such as dynamic ON-resistance behaviour, breakdown mechanism, interplay of various trap/defect states, time dependent failure, and physical mechanisms governing safe operating area, electrostatic discharge behavior, etc. Using detailed experimentations, his group probed these fundamental performance and reliability showstoppers and developed physical insights explaining the root cause of the problem. These insights helped his group devise methods to engineer HEMTs for improved reliability and performance. Besides, his group discovered a unique way to engineer the gate stack of these HEMT devices – by using a p-type dielectric – which enabled normally-OFF operation. These explorations enabled Prof. Shrivastava’s group to demonstrate high performance – highly reliable (and India’s first) enhancement mode (e-mode) HEMT device and GaN diodes for next-generation power electronics applications and monolithically integrated power electronics concepts.

On the Si LDMOS front, Prof. Shrivastava’s has been instrumental in developing and enabling integrated Si LDMOS devices, which in today’s System on Chips (SoCs) and Power SoCs (Automotive ICs) covers ~40% and ~70% of the chip area, respectively. Since 1970 various integrated high-power Si devices have been proposed for such applications. However, they used to fail under high current switching conditions, which seriously hampered the usefulness of these devices for advanced SoC products. The physical cause for such failures was not known to scientists before. For example, various groups speculated that high current failures in LDMOS devices are stochastic in nature; however, nominee’s work revealed the deterministic and unified nature of these failures across various types of integrated Si LDMOS devices. These insights enabled the nominee to invent a new class of robust & high-performance LDMOS devices, which can be found in advanced SoCs today. His research also changed the perception that robustness and performance cannot be achieved together, particularly for the high power-high frequency application. Going a step further, he invented and designed the first high-power devices for FinFET technology. SoC design in these very advanced CMOS technologies was not expected soon. However, recent device inventions resulting from his work have enabled semiconductor industries to design and manufacture SoC in FinFET and related CMOS nodes.

Work Experience

  1. Associate Professor, Department of Electronic Systems Engineering, Indian Institute of Science Bangalore (June 2019 – Present).
  2. Assistant Professor, Department of Electronic Systems Engineering, Indian Institute of Science Bangalore (September 2013 – May 2019).
  3. Staff Engineer: Intel Corp. (MCG), Munich, Germany (April. 2013 – August 2013).
  4. Senior Engineer: Intel Corp. (MCG), Munich, Germany (Sep. 2011 – March 2013).
  5. Senior Engineer: Infineon Technologies, USA (Sep 2010 to Jan 2011) and Intel Corp. (MCG), USA, (Feb 2011 to Sep 2011).
  6. Visiting Scholar: Infineon Technologies, Munich, Germany. April 2008 to Oct 2008 and again from May 2010 to July 2010.

Entrepreneurial Experience

  1. Co-Founder, AGNIT Semiconductors Pvt. Ltd.
  2. Investigator, Gallium Nitride Ecosystem Enabling Centre and Incubator (GEECI)

Research Interest

Research Focus

My group works on the science and technology of electron devices, having focus on power semiconductor devices as well as nanoscale / beyond Si CMOS for SoC applications. Given a strong focus on the semiconductor technology for the future electronics, we also work on a multitude of science threads like (i) physics of semiconductor device reliability, (ii) electro-thermal / electron – phonon interaction in beyond Si materials / devices, (iii) thermometry and thermal / phonon transport in these materials / devices. Both the science and technology threads are briefed in figure below.

Research Interest and Thrust Areas

  • Graphene, Carbon Nanotubes and novel 1D/2D materials
  • Nanoscale device design and modeling
  • Beyond CMOS
  • Light Weight and Flexible High Performance Electronics
  • Device-circuit co-design
  • Electrothermal modeling
  • On-chip ESD Protection
  • Gallium Nitride (GaN) High Electron Mobility Transistors (HEMT)
  • LDMOS and DeMOS HV/Power device design
  • Nanotechnology for Mobile Systems
  • Analog Memory for Neuromorphic applications

Research Highlights

1. Understanding quantum nature of graphene-metal contact:

Quantum nature of graphene’s interface with outside world was explored and revealed. We studied how the overlap of atomic orbitals between Carbon and metal atoms affects the graphene-metal interface. The study has enabled us to invent novel techniques to engineer graphene contact that has the lowest recorded contact resistance. Record low contact resistance (and several technological advancements from the group) allowed us to demonstrate graphene transistors with record high performance. (This work in IEDM-16 broke several records – including the one published by IBM T. J. Watson’s group.)

2. Deeper insights into Electron-Phonon Transport Probed at nano-second time scale

We have developed a new technique to probe electron – phonon interaction at nano-second time scales. The idea is to isolate carrier transport from external or induced perturbations, which develop as a function of time, example phonon bath, and systematically study dynamics of electron transport. This is the first time any research group has developed and reported such a technique. Using this method we have reported, for the first time, (i) remote joule heating of cold contact and its impact on carrier transport through 1D and 2D materials, (ii) time constant of contact and channel annealing, (iii) dynamics of thermal failure and (iv) changeover from ballistic to diffusive transport attributed to scattering induced phonon bath at the nanosecond time scale. (We have published these works at forums like IEEE T-ED, APL, IEEE IRPS, and EOSESD Symposium)

3. Breakthrough in Nanometer scale transistor technology

My group has demonstrated a new transistor design which can significantly improve the chip performance and it’s scalability beyond 10nm technology node. It works at lower voltages, draws 15 times less charge in idle state and offers higher frequency performance. These factors ensure longer battery life, smaller chip area (lighter), lower cost and higher speed. This new device is expected to reduce chip cost by four to five times for IoT applications when compared to current day technology. In simple terms it offers a newer technology which is cheaper and can be manufactured without putting capital, that is newer manufacturing plants, and at the same time it offers significantly better performance and scalability. This was published in IEEE T-ED.

4. New Class of Integrated Power Transistors:

For the first time, a novel Drain extended tunnel FET device (DeTFET) is disclosed, while addressing need for high voltage / high power devices for System on Chip and automotive applications in beyond FinFET technology nodes. Operation of the proposed DeTFET device is presented with physics of band-to-band tunnelling and associated carrier injection. Device’s intrinsic (DC/switching), analog and RF performance compared with state of the art drain extended NMOS device (DeNMOS) shows that the proposed device offers 15× better subthreshold slope, 8× lower OFF state leakage, 2× higher ON current, absence of channel length modulation and drain induced barrier lowering, while keeping 2.5× lower threshold voltage. This results into significantly better ON resistance for a range of gate voltages, higher transconductance, orders of magnitude higher intrinsic transistor gain and better RF characteristics, when compared to the DeNMOS device. The patented (and later published in IEEE T-ED) device is expected to improve the performance of future power ASICs.

5. ESD reliability of newer material-based transistor technologies

ESD is considered to be one of the most fundamental reliability issue associated with semiconductors. We have explored ESD reliability of graphene, CNT, Pentacene and a-Si:H like new material-based devices and GaN based high electron mobility transistors. My group has published majority of papers (at forums like IEEE T-ED, IRPS, ISPSD and EOSESD Symposium) in this area.

6. Performance and reliability advancement of LDMOS devices

It’s been over 40 years when the first power MOSFET was invented. However, till the last decade, performance and reliability of these devices was considered to be an independent phenomenon and was always studied / addressed independently. In our works, for the first time, we have attempted to find common design knobs to tackle both the challenges. In this direction, we have (i) unified physics of quasi-saturation in power MOSFETs, which was considered to be a fundamental bottleneck; (ii) using the unified physics we have shown different ways by which quasi-saturation can be mitigated, which improves device performance and (iii) have come-up with few design proposals, which improves the device performance as well as reliability. These works have changed the way power MOSFETs were designed and are now being used in integrated circuits. (We have published these works at forums like IEEE T-ED, IRPS, IEDM, SISPAD, ISPSD and EOSESD Symposium. Majority of our findings have been adopted by Industry.)

7. Record High Performance 600V e-mode GaN HEMT Technology

For the first time, a high- κ ternary gate oxide has been demonstrated as a potential candidate for achieving e-mode operation in AlGaN/GaN HEMTs. The ternary oxide was found to be similar to p-GaN gate for achieving e-mode HEMT operation. However, it allowed better channel control as a thin ternary oxide in conjunction with partial recess was capable to achieve a threshold voltage of 0.5V. Using the developed gate oxide, record high performance 600V class of e-mode device has been demonstrated with ON current ~400mA/mm, subthreshold slope of 73mV/dec, Ron = 9 Ω-mm, interface trap density < 1010 mm-2eV-1 and gate leakage below 200nA/mm at the OFF state breakdown. Based on experimental finding, a hybrid gate stack which combines pGaN technology with the developed dielectric for e-mode operation, has been proposed.

8. Deeper Insights in GaN HEMT Reliability Issues

Through 5 papers in IEEE IRPS (2016 – 2019) and 1 in IEDM (2018) we have revealed deeper insights and have highlighted fundamental issues related to reliability physics of GaN HEMTs. Besides, we have also developed deeper insights into the physics and role of C-doping of GaN buffers in AlGaN/GaN HEMTs. These insights have allowed us to engineer C-doping profile across GaN Epi-stack with improves the breakdown voltage as well as mitigates current collapse phenomena at the same time, without compromising on leakage current (The work on C-doping was published in IEEE T-ED).

9. High Performance 2D Material FET Technology

For the first time, atomic orbital overlap engineering for TMDs is proposed, which significantly improves the overall transistor performance without any hidden compromise. Understanding low temperature decomposition of H2S on TMD surface and quantum chemistry between transition metals, chalcogenides & contact metals have enabled the proposed atomic orbital overlap engineering to improve channel as well as contact performance and passivate/cure dangling bonds present in defected regions. These collectively have improved MoS2, WS2, MoSe2 and WSe2 FET’s characteristics by significant margins. Record high ON current for WS2 FET (240 mA/mm), at room temperature is demonstrated. Moreover, an overall record high performance improvement is achieved for MoS2, WS2, MoSe2 and WSe2 The proposed approach has been validated statistically across large set of devices. Besides, a novel way to get p-channel operation in WSe2 devices have been demonstrated.

Funding and Sponsors

Sr. No.

Project Title

Agency

Value in Rs. (Lacs)

Duration

PI/Co-PI/Investigator

1

Institute Seed Grant for the Establishment of Advance Nanoelectronics Device & Circuit Research Laboratory

IISc

34

Oct 2013 – Sep 2014

PI

2

Demonstration of Graphene based RF Transistors

DRDO (SSPL)

10

June 2014 – Oct. 2014

PI

3

Exploration of Carrier Transport and Contact Resistance Behaviours in Carbon Nanotube and Graphene Devices Using Nanosecond Time Scale Charge Bust

DST (SERB)

51

July 2014 – June 2017

PI

4

Investigation on GaN devices for power electronic switching applications and design and development of a high frequency GaN convertors topology

NaMPET Phase-II

191

Oct. 2014 – March 2017

Co-PI

5

Advance Nanoscale Characterization Facility

IISc

110

Jan 2015 – Sep 2015

PI

6

ESD Reliability of sub-14nm node technologies

Intel, Germany

150K USD

Dec 2015 – Nov. 2018

PI

7

12th Plan Grant to Develop Laboratory Space

IISc

5

Sep 2016 – March 2017

PI

8

Technology Development for 600V Normally – OFF Gallium Nitride Transistor for Reliable Power Electronic Systems

DST (TSDP)

1028

May 2016 – August 2020

PI

9

Graphene Based THz Transistor Technology

DRDO (ERIPR)

500

March 2017 – March 2023

PI

10

High Voltage & ESD Device Development & Enablement in SCL’s 180nm CMOS Technology

IMPRINT

300

March 2017 – March 2021

PI

11

Detailed Project Report on GaN Foundry

DeitY

60

March 2016 – Sep. 2016

Co-PI

12

Power-scalability of Advance Semiconductor Devices from ESD time domain to DC

Texas Instruments (USA)

165K USD

Oct 2017 – Sep 2020

PI

13

2D Material Based Transistor Technology

NNeTRA program of MeitY
(Under CEN-III)

150 (sub-project)

April 2018 – March 2022

Co-PI
(PI of sub-project)

14.

Exploratory Project under IOE

IISc/MHRD

200

August 2019 – March 2020

PI

15.

Advance Nanoscale Characterization Facility (II)

IISc (MHRD)

150

March 2018 – Sep. 2018

PI

16.

Graphene Based Heat Spreader Technology

IMPRINT-II

140

PI

17.

HV ESD Protections Design for On-Chip IEC ESD

TI, USA

210K USD

Oct. 2020 – Sep. 2023

PI

18.

Development of New TVS Product and Technology

AOS, USA

450K USD

Nov. 2020 – Oct. 2023

PI

19.

Performance and Reliability Co-Design of e-mode GaN HEMTs

DST, SERB (CRG)

80

September 2021 – August. 2024

PI

20.

A Novel Memory Synapse Technology for Neuromorphic Computing

DST, DERB

380

March 2022 – Feb 2027

PI

21.

Development of On-board (In-Vehicle) Fast DC Chargers Using High-Speed GaN HEMTs for Two-Wheeler (2W) Electric Vehicles

MeitY

450

April 2022 – March 2024

PI

22.

Development of Rugged 30A/650V e-mode Power HEMT Technology and Fast 1kW DC Charger using the in-house Developed Power HEMT

DST, AMT

990

April 2022 – March 2025

PI

Total Sanctioned Funding Feb. 2022

5800
Lakhs

   

Facility

Research Facility in MSDLab

This is a ~25 Crore worth facility. The unique capabilities of this facility are being extensively utilized, not just by PhD students in MSDLab, but also by staff and students from several other departments. In general, this facility has helped develop several technologies such as graphene and 2D materials technology, high power Gallium Nitride technology, organic electronics and Si based power technology. The users can independently handle the tool post a systematic training.

1. Manual Probe Station

Lab has 2 manual probe stations. The tool allows holding and probing samples of 1cm size to 8-inch wafers. The probe station houses a high-end microscope with magnification up-to 1000, which allows probing nano-meter sized devices for DC and RF tests at temperatures between 300K to 500K. Besides, its capable of measuring ultra-low currents, as well as very high currents and voltages. The vibration free table with pneumatic isolation using a low noise air compressor allows high precision probing of the devices.

2. Semi-automatic Probe Station

It enables automatic DC and RF device characterization (up to 110 GHz), wafer-level reliability, e-test, modelling, or yield analysis. It is equipped with probe station control software to automate the measure 1000s of devices with a single click.

3. Range of Wafer Level Electrical Characterization Equipment

The facility has the following electrical characterization tools.

Equipment Type

Make

Model

Specification

SMU (4 Nos)

Keithley 2400

Keithley 2400

General purpose SMU (100V, 1A)

SMU (2 Nos)

Dual Channel SMU

Keithley 2635B

Single Channel SMU capable of 1A DC (10A Pulse), 200V.

SMU

Dual Channel SMU

Keithley 2636B

Dual Channel SMU capable of 1A DC (10A Pulse), 200V

SMU

Dual Channel SMU

Keysight

Dual Channel SMU capable of 1A DC, 200V

HC SMU (2 Nos)

High Current SMU

Keithley 2651A

High Current SMU (Upto 50A in pulsed mode, 20A in DC mode)

HV SMU (7 Nos)

High Voltage SMU

Keithley 2657A

High Voltage SMU (Upto 3kV)

CV Meter

CVU

Keithley PCT-CVU

High voltage capacitance measurements

Switching Matrix

Switching Matrix

Keithley 707B

Six-slot semiconductor switch mainframe (8 input and 36 output ports)

High Power interface panel

Panel

Keithley 8020

Interface between the Parametric Curve Tracer (PCT), SMUs, probe station and test fixtures for wafer level high power measurements.

PNA -X Network Analyzer

VNA

Keysight N5247

67 GHz PNA- X for Semiconductor Characterization

Parametric Curve Tracer (2 Nos)

4200

4200A-SCS

Parametric curve tracer with automation capability and switching matric for semiconductor device characterization. It consists of 6 medium power SMU, 1 CVU and 2 pulse measurement units.

FFT Spectrum Analyzer

SR760

SR760

Single-channel 100 kHz FFT spectrum analyzer

Digital Phosphor Oscilloscope

DPO

DPO 70404C

4 GHz digital oscilloscope

High speed pulse generator

HSPG

AVR-E3-B-W3

100 V, 1 ns to 5000 ns pulse generator

Arbitrary Function Generator (3 Nos)

AFG

AFG1022

µHz to MHz, mV to 10 V, dual channel function generator

4 Channel Digital Storage Oscilloscope (2 Nos)

DSO

TBS1154

150 MHz, 4 channel oscilloscope

Lock-in Amplifier

MFLI

MFLI

500 kHz Lock-In Amplifier

4. Transmission Line Pulsing

Transmission line pulse setup is used to generate electrical pulses at a very high frequency with high amplitudes. At these frequencies, wavelength of electrical signal reaches the length scales of the testing setup and a proper pulse shaping is difficult. Due to these issues, a conventional SMU cannot be used for this purpose and a specialized strategy is needed. The TLP pulse generator works on the principle of transmission line pulsing technique. The TLP generator can generate pulses in pulse width range of 1ns-1.5 us with a maximum voltage level of 2 kV.

5. Micro Raman, EL/PL Setup with UV and Visible Lasers

Raman spectroscopy works on the principle of inelastic scattering of light by a material. As the light is applied on a material, the following interactions take place: Rayleigh scattering, Stokes scattering and Anti-stokes scattering.  Raman setup works on the principle of stokes and anti-stokes scattering, and is used to study chemical and vibrational properties of a material. A laser source with a pre-determined wavelength and power density is used and a charge couple detector is used to capture photons emitted from the material upon interaction with light. The setup has the following two light sources: (1) DPSS, green-colour, 532 nm and (2) UV light, 325 nm. The setup also comprises of electrical part used to study material change with stress application. A cryogenic pump, with an ability of cool down as low as 4K, is integrated with the Raman setup to study device interactions at extremely low temperatures. This study is used to study ambient interactions, photoluminescence, electroluminescence, impact of electrical stress on chemical properties and low temperature vibrational properties of a material.

7. Custom Setup for 2D Material Based Stamping and Device Fabrication inside Glovebox

This custom developed tool provides an inert environment for fabrication of devices using materials sensitive to oxygen and moisture (less than 1ppm of Oxygen and moisture). This enables development of heterostructures using dry transfer setup called stamping stage having high magnification (2000x) microscope and range of nano-manipulators, provides an efficient way to explore fundamental properties and application specific behaviour of various potential materials for electronic applications. The setup also consists of thermal evaporator for metal deposition and wet-bench. Such an assembly of stamping stage and thermal evaporator inside inert atmosphere enables an ultra-clean process for device fabrication.

8. 3K Ultra Low Vibration Close-Loop Cryocooler for Optical and Electrical (DC & RF) Measurements

This tool allows loading devices under ultra-low temperature (3K) condition and enables optical as well as electrical excitations / measurements.

9. L-N2 Semi-automatic Probe Station

This is a L-N2 based semi-automatic probe station. The tool enables DC and RF device characterization, wafer-level reliability, e-test, modelling, or yield analysis for a temperature ranging from 77K to 550K. It is equipped with a probe station control software to automate measurements for 1000s of devices.

10. Deep Level Transient Spectroscopy

This tool allows probing deep level defect / trap states in materials.

11. Thermo Reflectance Spectroscopy

This tool allows probing temperature across a nanoscale device with sub-400nm special resolution and sub-ns time resolution.

12. Wafer Level Semiconductor Device Reliability Characterization Suit

This tool allows to study high field reliability behaviour of semiconductor devices such as HCI, TDDB, NBTI, PBTI and other similar issues in emerging devices.

13. High End Computational Cluster

With over 250 Cores and 6TB RAM, this is among the most powerful cluster being used for TCAD simulations and Atomistic computations.

14. Parametric Curve Tracer with sub-50ns pulse I-V measurement capability

The lab has two such systems from Keithley (Keithley 4200 SCS), which consists of 6 medium power SMUs (each), capacitance-voltage measurement unit and two sets of pulse measurement units (PMU). It allows measurement from fA to A. It can also measure pulse I-V characteristics with 50ns pulse width.

15. 1/f Noise Measurement Setup

This enables 1/f Noise measurements in range of devices.

16. 3-Omega setup for thermal conductivity measurements

 

17. Atomic Force Microscopy (AFM)

AFM with additional modes such as CAFM, KPFM, SThM, STM, SCM, SSRM, IV Spectroscopy, Lthography, Piezoelectric studies, etc which offers flexibility to perform surface studies and material response to electrical studies.

18. Pulse Raman, Wafer Scale Electroluminescence Mapping, Dark Field Microscopy

Setup for pulsed Raman is available for precise material studies. Electroluminescence mapping, dark field microscopy enhances the surface observation capabilities for identification and processing of novel crystals based devices.

Research Group

Postdoctoral Fellow

  1. Kalyan Jyoti Sarkar (PhD IITKgp, DST SERB NPDF)
  2. Ashita Kumar (AOS Fellow)
  3. Satendra Kumar Gautam (PhD IITR, AOS Fellow)
  4. Vipin Joshi (PhD IITJ)
  5. Nikhil K S (PhD IITM, Assistant Professor, NIT Calicut)
  6. Asha Yadav (PhD IITG, Currently with University of Calgary)
  7. Jhnanesh Somayaji (Currently with Global Foundry)
  8. Ajay (Currently with Global Foundry)

PhD Students

  1. Aadil Bashir Dar (NIT Srinagar, IIT Kanpur)
  2. Harsh Raj (B-Tech + M-Tech, IIT Kanpur, PMRF)
  3. Mitesh Goyal (B-Tech, NIT Trichy, Associate Director, Samsung)
  4. Subhajit Majumder (B-Tech, IIST Trivandrum, Senior Engineering Scientist, ISRO)
  5. Mehak Ashraf Mir (JMI, NIT Srinagar)
  6. Asif Altaf Shah (M-Tech, NIT Srinagar)
  7. Mohammad Ateeb Munshi (M-Tech, NIT Srinagar)
  8. Rasik Rashid (M-Tech: NIT Srinagar)
  9. Anand Rai (B-Tech: NIT Patna, PMRF, Gate Rank: 113)
  10. Utpreksh Patbhaje (B-Tech: IIIT Jabalpur, PMRF, Gate Rank: 925)
  11. Rupali Verma (B-Tech: NIT Patna, PMRF)
  12. Rajarshi Roy Chaudhuri (M-Tech: IIEST Shibpur, Inspire Fellow)
  13. Monish Murali (B-Tech: PESIT, GATE Rank: 397, TI Fellow)
  14. Sayak Dutta Gupta (M-Tech: IIEST Shibpur, Inspire Fellow)
  15. Jeevesh Kumar (B-Tech: NIT Trichy, CSIR-UGC NET Rank: 71, CSIR Fellow, June 2022)
  16. Harsha B (B-Tech: GEC Trissur, GATE Rank: 414, Graduating: June 2021)
  17. Hemanjaneyulu Kuruva (2021, M-Tech: IISc Bangalore, Visvesvaraya Fellow, Now with Global Foundry)
  18. Ansh (2021, B-Tech: NERIST Itanagar, Joining University of Texas at Austin as a Postdoc Fellow)
  19. Kranthi N. K. (2021, M-Tech: NIT Calicut, Visvesvaraya Fellow, Now with Texas Instruments)
  20. Ankit Soni (2021, B-Tech: NIT Hamirpur, GATE Rank: 864, Visvesvaraya Fellow, Now with Global Foundry)
  21. Rajat Sinha (2021, B-Tech: BIT Mesra, GATE Rank: ……., Now with Global Foundry)
  22. Bhawani Shankar (2020, M-Tech: BITS Pilani, Now with Stanford University as a Postdoc Fellow)
  23. Adil Meersha (2020, B-Tech: NIT Calicut, GATE Rank: ……, Now with University of Cambridge as a Postdoc Fellow)
  24. Abhishek Mishra (2020, M-Tech: IIITM Gwalior, Now with University of Bristol as a Postdoc Fellow)
  25. Milova Paul (2020, M-Tech: DTU Delhi, Now with Global Foundry, Singapore)
  26. Sampath B (2020, M-Tech: NIT Nagpur, Now with Global Foundry, Singapore)

Teaching and Workshops

#
Course No.

Course title (Click to see Syllabus)

Nature

Term

1

E3 282 Basics of Semiconductor Devices and Technology

Core

August

2

E3 200 Microelectronics Lab

Core

August

3

E3 275 Physics and Design of Transistors

Soft Core

Jan

4

E3 274 Design of Power Semiconductor Devices

Soft Core

Jan

5

E3 271 Reliability of Nanoscale Circuits and Systems

Soft Core

Jan

6

E3 301 Design of Power Semiconductor Devices

Elective

Jan

Conferences and Workshops Hosted :

  1. IEEE EDS/SSCS Bangalore Chapter Chair (Since Dec 2015). In this role I have hosted more than 25 international experts from around the world (see list enclosed).
  2. 3rd India ESD Workshop (Feb 2019): This was the third edition of India ESD workshop, which ran for 2 days. This time it was driven by VLSI industry in Bangalore with a total (paid) participation above 200. The workshop hosted 4 keynote talks by renowned international ESD experts, 2 tutorial talks, 14 invited talks and 15 poster presentations.
  3. Organized 3rd IEEE CONECCT (March 2013), which was attended by over 250 participants with around 100 Oral and poster papers. The conference ran for 2 days with 4 keynote talks and 4 parallel technical sessions.
  4. Organized 4th IEEE ICEE (Dec 2018), which was attended by over 650 participants. The conference ran for 4 days with over 20 tutorial talks and 8 keynote talks. Besides, ICEE had 160 invited talks, 102 Oral papers and 125 poster papers, divided in 10 parallel technical sessions.
  5. 2nd India ESD Workshop: This was the second edition of India ESD workshop, as part of India ESD forum formed in year 2016. This time it was much more professionally organized with over 80 registrations. The event was covered by ESD Association’s (USA) newsletter, IEEE EDS newsletters, as well as several online media houses, which are published internationally.
  6. Offered a 3 day ESD course / workshop to X-Fab engineers in Kuching, Malaysia. This was fully funded by X-Fab and was registered by over 25 X-Fab engineers.
  7. 1st India ESD Workshop: 1 day workshop on on-chip ESD design, hosted in IISc. Single-handedly formed a forum or nationwide special interest group called “India ESD Forum”, which today has over 60 industry members. This workshop was attended by over 30 industry senior engineers / managers. The event was covered by ESD Association’s (USA) newsletter, which is published internationally.
  8. ESD Design Essentials: 2 day workshop hosted at Hotel Oberoi, Bangalore. This was technically and financially sponsored by ESDA, USA.

Recognitions

Professional Recognitions, Awards, and Fellowships:

  1. SwarnaJayanti Fellowship, DST, 2021 – 2026
  2. VASVIK Award, Year 2021
  3. Abdul Kalam Technology Innovation National Fellowship, INAE, 2021 – 2026
  4. National Academy of Sciences, India, (NASI) Young Scientist Platinum Jubilee Award – 2018
  5. Indian National Academy of Science (INSA) Young Scientist Award, 2018
  6. Indian National Academy of Engineering (INAE) Innovator Entrepreneur Award 2018 (Special commendation)
  7. Indian National Academy of Engineering (INAE) Young Engineer Award, 2017
  8. 2015 IEEE EDS Early Career Award, one of the highest honors given by IEEE Electron Device Society (EDS).
  9. INAE Young Associate (since 2017)
  10. Indian Academy of Sciences (IASc), Young Associate, 2018 – 2023
  11. Department of Electronics & Information Technology (DeitY), Govt. of India, Young Faculty Fellowship for the duration of 2016 – 2020.
  12. Outstanding Paper Award, 38th EOSESD Symposium, 2017 and VLSI Design Conference, Jan. 2017
  13. Editor for Elsevier Microelectronic Reliability (2018 – 2020)
  14. TR35, 2010, Young Innovator Award. Technology Review’s TR35 list by Massachusetts Institute of Technology recognizes the outstanding innovators under the age of 35 each year. Received on March 8, 2010
  15. Award for Excellence in Thesis Work, IIT Bombay-2010, received on 6th August, at the 48th convocation of IIT Bombay.
  16. IIT Bombay – Industrial Impact Award, for pursuing research work that caused maximum industry impact. Received on September 6, 2010 by Dr. N. Mukunda, who is a prominent Indian scientist.
  17. Best Research paper Award, Intel Asia Academic Forum 2008, Oct 2008, Taipei, Taiwan
  18. Infineon Fellowship, Duration: November 2008- July 2010
  19. Technical Program Committee (TPC) IEDM and IRPS are the two most prestigious conferences
    • IEEE International Electron Device Meeting (IEDM), USA, 2018 – 2019
    • IEEE International Reliability Physics Symposium (IRPS), USA 2017 – 2021
    • EOSESD Symposium, USA: 2012 – 2021 (Sub-committee chair in 2014 & 2017)
    • IEEE EDTM, Singapore 2019
    • IEEE ESSDERC, Europe: 2014 – 2016
    • IEEE ESREF, Europe, 2019
    • IEEE ICEE – 2018 (TPC Chair), 2020 (General co-Chair), 2022 (General Chair)
    • IEEE CONECCT – 2018 (Gen. co-Chair and TPC Chair)
    • IEEE VLSI Design 2014 & 2015 (Vice-chair, “Device and Process Technology” session)

Publicity / Popular Recognition

With IISc Affiliation:

Economic Times: https://auto.economictimes.indiatimes.com/news/auto-components/iisc-technology-can-address-automotive-chip-shortage/89987058
News 18: https://www.news18.com/news/auto/researchers-at-iisc-collaborating-to-provide-solution-for-chip-shortage-in-auto-industry-4837550.html
Indian Express: https://indianexpress.com/article/cities/bangalore/iisc-bengaluru-research-chip-shortage-7800829/
Bhaskar: https://www.bhaskarlive.in/iisc-technology-can-address-automotive-chip-shortage/
My News 24×7: https://mynews24x7.in/iisc-technology-can-address-automotive-chip-shortage-et-auto/
News Network: https://todaynewsnetwork.in/indian-institute-of-science-technology-could-help-address-automotive-chip-shortage/
Times Bureau: https://thetimesbureau.com/to-solve-chip-shortages-iisc-researchers-have-developed-a-resilient-high-voltage-automotive-technology-platform-202203/
Business Bytes: https://www.buzinessbytes.com/technology/iisc-technology-can-address-automotive-chip-shortage/
Lokmat Times: https://www.lokmattimes.com/technology/iisc-technology-can-address-automotive-chip-shortage/
Gadgets Now: https://www.gadgetsnow.com/tech-news/iisc-technology-can-address-automotive-chip-shortage/amp_articleshow/89991291.cms
Ahmedabad Mirror: https://ahmedabadmirror.com/iisc-technology-can-address-automotive-chip-shortage/81823583.html
India Today: https://www.indiatoday.in/education-today/news/story/iisc-bangalore-s-swarnajayanti-awardee-is-researching-on-materials-to-make-computers-more-efficient-1907180-2022-02-01
DST: https://dst.gov.in/swarnajayanti-awardee-bangalore-working-materials-can-make-computers-more-efficient
Telegraph: https://www.telegraphindia.com/edugraph/news/iisc-bangalore-professor-researches-on-mimicking-functions-that-the-brain-can-perform-rapidly/cid/1850185
Business Insider: https://www.businessinsider.in/science/research/news/iisc-scientist-develops-material-that-can-help-computers-mimic-brain-like-functions/articleshow/89263106.cms
Deccan Herald: https://www.deccanherald.com/science-and-environment/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function-1076764.html
Kalinga TV: https://kalingatv.com/technology/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function/
Gadgets Now: https://www.gadgetsnow.com/tech-news/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function/amp_articleshow/89264611.cms
National Herald: https://www.nationalheraldindia.com/amp/story/science-and-tech/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function
Ahmedabad Mirror: https://ahmedabadmirror.com/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function/81819733.html
Social News: https://www.socialnews.xyz/2022/01/31/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function/
Tripura India: https://www.tripuraindia.in/update/index/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function
Block One Daily: https://blockonedaily.com/iisc-scientist-brings-out-material-that-can-help-computers-mimic-human-brain-function/
Mangalore Mirror: https://www.mangaloremirror.com/swarnajayanti-awardee-from-bangalore-working-on-materials-that-can-make-computers-more-efficient/
Indian Express: https://indianexpress.com/article/cities/bangalore/bengaluru-scientists-swarnajayanti-fellowships-7613187/
IISc Press: https://iisc.ac.in/events/35034/
Aljazeera: https://www.aljazeera.co.in/business/three-bengaluru-scientists-awarded-swarnajayanti-fellowships/
New Indian Express: https://www.newindianexpress.com/cities/bengaluru/2021/nov/09/three-bengaluru-scientists-get-swarnajayanti-fellowships-2381168.html
Republic World: https://m.republicworld.com/india-news/education/17-scientists-awarded-swarnajayanti-fellowships-for-innovative-research-ideas.html
Business Bytes: https://www.buzinessbytes.com/news/national-news/swarnajayanti-fellowship-awarded-to-scientists-from-bangalore/
Ministry of Science & Technology (English Release): https://pib.gov.in/PressReleasePage.aspx?PRID=1705691
Ministry of Science & Technology (Hindi Release): https://pib.gov.in/PressReleasePage.aspx?PRID=1705750
DST: https://dst.gov.in/new-technology-high-electron-mobility-transistor-will-make-india-self-reliant-power-transistor
Bangalore Mirror: https://bangaloremirror.indiatimes.com/bangalore/cover-story/e-ncredible-india/articleshow/81575854.cms
Kashmir News: https://kashmirnewsbureau.com/scientists-from-bangalore-develop-highly-reliable-hemt/
Swarajya Magazine: https://swarajyamag.com/insta/indian-scientists-develop-indigenous-normally-off-high-electron-mobility-transistor-for-power-electronics
News20: https://news20-20.com/new-technology-for-hemt-developed/
Adda247: https://www.adda247.com/upsc-exam/daily-gist-of-the-hindu-pib-indian-express-and-other-newspapers-18-march-2021/
Rajya Sabha TV: https://www.youtube.com/watch?v=ASJ2H-NV7hw
Research Matters: https://researchmatters.in/news/iisc-develops-india%E2%80%99s-first-e-mode-gallium-nitride-power-transistor
Times of India: https://timesofindia.indiatimes.com/home/science/iisc-faculty-change-game-with-indias-first-e-mode-gallium-nitrade-power-transistor/articleshow/69661844.cms
Electronic for You: https://academia.electronicsforu.com/iisc-researchers-develop-indias-first-e-mode-gallium-nitride-power-transistor
Northbound: http://www.northbound.co.in/engineering-phd/
Research Matters: https://researchmatters.in/news/iisc-research-pushes-reliability-and-operating-limits-ultra-dense-finfet-system-chips
EE Herald: http://www.eeherald.com/section/news/owns20171225001-india-ee-edu.html
Research Matters: https://researchmatters.in/article/inae-announces-young-engineer-awards-2017
India DST: https://indiadst.wordpress.com/2017/01/20/iisc-researchers-develop-new-graphene-based-transistor-technology/
Scientifist: http://scientifist.com/iisc-researchers-graphene-electronics/
Indian Express: http://indianexpress.com/article/technology/science/breaking-the-graphene-barrier-4465396/
Bangalore Mirror: http://bangaloremirror.indiatimes.com/bangalore/others/iisc-can-make-your-wifi-1000-times-faster/articleshow/56091767.cms
IISc Press: https://researchmatters.in/article/iisc-scientists-new-discovery-yields-giant-leap-graphene-transistor-performance
The Better India: http://www.thebetterindia.com/79060/iisc-working-making-wifi-1000-times-faster/
UC News: http://www.ucnews.in/news/702-513932134192309/a-team-of-researchers-from-iisc-bangalore-could-make-our-wifi-1000-times-faster.html
Yahoo: https://in.news.yahoo.com/team-researchers-iisc-bangalore-could-095934372.html
Indian 364: http://www.indian364.com/technology/26961/Breaking-the-graphene-barrier
Research Matters: https://researchmatters.in/article/iisc-scientists-new-discovery-yields-giant-leap-graphene-transistor-performance
Rajya Sabha TV: https://youtu.be/k9u2Ji9Vlbk
Bangalore Mirror: http://www.bangaloremirror.com/bangalore/others/New-transistor-design-is-a-breakthrough/articleshow/49897633.cms
Indian Express: http://indianexpress.com/article/technology/technology-others/from-the-lab-a-new-device-for-more-efficient-phones-computers/
IISc Press: http://iisc.researchmedia.center/article/iisc-researcher%E2%80%99s-new-transistor-design-%E2%80%93-breakthrough-chip-technology
Indian Express: http://www.newindianexpress.com/cities/bengaluru/IISc-Prof-Wins-Major-Global-Award/2015/10/29/article3102225.ece
Deccan Herald: http://www.deccanherald.com/content/515146/bengaluru-scientist-wins-coveted-ieee.html
Hindu: http://www.thehindu.com/news/cities/bangalore/honour-for-iisc-professor/article7816056.ece
Global Indians: http://www.globalindian.indiaincorporated.com/iisc-prof-wins-major-global-award/
IEEE: http://eds.ieee.org/early-career-award.html
IISc Press:: http://iisc.researchmedia.center/article/iisc-professor-wins-major-international-award
Deccan Herald: http://www.deccanherald.com/content/509822/iisc-faculty-devises-technology-shrink.html
News Central: http://newscentral.exsees.com/item/8563b69c9b5b9519487c36e18dcedb90-f39db1effc9ea34e1d52a76b94b3ea02
Gas & Electricity: http://gaselectricity.in/iisc-faculty-devises-technology-to-shrink-power-electronic-systems
Daily Hunt: http://m.dailyhunt.in/news/india/english/deccan-herald-epaper-deccan/iisc-faculty-devises-technology-to-shrink-power-electronic-systems-newsid-45850179
Nyooz: https://www.nyoooz.com/news/bengaluru/245362/iisc-prof-wins-major-global-award/
GK Today: https://www.gktoday.in/quiz-questions/who-became-the-first-indian-to-bag-ieee-electron-devices-society-early-career-award/

Before joining IISc:

Technology Review: http://www2.technologyreview.com/tr35/profile.aspx?TRID=860
DNA: http://www.dnaindia.com/india/report-iit-b-makes-it-to-mit-s-top-innovators-list-1361475
Deccan Herald: http://www.deccanherald.com/content/58465/beyond-classroom.html
Indian Express: http://www.indianexpress.com/news/towards-smaller-better-gadgets/587650/0
NDTV: http://www.ndtv.com/news/sci-tech/iit_infineon_achieve_breakthrough_for_system-on-chip.php
EE Herald: http://www.eeherald.com/section/news/nw10000592.html
EE Times: http://www.eetimes.com/author.asp?section_id=36&doc_id=1284049
EE Times: http://www.eetimes.com/electronics-news/4083184/Infineon-Indian-researchers-claim-ESD-advance
Rediff: http://business.rediff.com/report/2009/apr/22/iit-achieves-breakthrough.htm

Invited Talks

  1. ESD Device Physics of Advance and Beyond CMOS Devices
      • Intel Corp., Munich, Germany (July 27th 2018)
      • Infineon Technology, Munich, Germany (July 28th 2018)
      • Intel Corp., Portland, USA (Sep 19th 2018)
      • NXP, Nijmegen, Netherlands (June 29th, 2018)
  2. The Future of World Electronics and the Possible Role India Can Play
      • Bangalore Nano, March 2022
      • IIT Indore, March 2022
      • IIT Patna, Dec 2021
      • Distinguished Lecture, IEEE SJC EDS Chapter, Oct. 2021
      • IIIT Kancheepuram, Oct. 2021
      • TBI CPDMED CEFC Design Manufacturing and Entrepreneurship Series, Aug. 2021
      • Distinguished Lecture, IEEE CAS Chapter, Feb. 2021
      • Distinguished Lecture, NIT Jalandhar, Sep. 2020
      • Distinguished Lecture, IEEE Bangalore Section, June 2020
      • IEEE Mini-Colloquium, Delhi University, Sep. 6th 2019
      • School of Physics at the IISER, Thiruvananthapuram, August 24th 2019
      • Workshop on Microelectronics and Information Security, SSPL, Ministry of Defense, Oct. 2018
      • 41st Annual event of KSCST (August 12th 2018)
      • Innovation Bazar, Western Digital (July 6th 2018)
      • IEEE Talk, Madras Chapter (Dec 26th 2017)
      • SSPL, DRDO (Oct. 2017)
      • IEEE Region – 10 Golden Jubilee Event, August 5th, 2017 (Key Note Talk)
      • 51st Computer Society of India Conference (Memorial Talk, Jan. 24th 2016)
      • IEEE Golden Jubilee Congress (August 2016)
      • IISc EECS Symposium (Feb 2016)
  3. Gallium Nitride Electronics: Design and Reliability
      • University of Padova, Padova, Italy (July 3rd 2018)
      • Infineon Technology, Villach, Austria (July 2nd 2018)
      • Online webinar organized by ESD Association USA, telecasted globally on 29th Nov. 2017.
      • IWPSD, Dec. 2017
      • ITC-India, July 2017
      • ICYRAM-2016, Dec. 14th 2016
      • Texas Instruments, Dallas, April 8th 2017
      • Semiconductor Complex Limited (SCL), Department of Space, May 2017
      • IEEE Conference, July 11th, 2017
      • International conference on Emerging Electronics, Dec. 5th 2014
  4. Record High Performance CVD Graphene Transistor
      • University of Budweiser, Munich, Germany, July 4th 2018
      • ISIF, Dec, 2017
      • IEEE International Conference on Emerging Electronics, Dec. 27th 2016
      • IIT Delhi, Jan 9th 2017
      • IIT Kanpur, Jan 10th 2017
  5. Performance & Reliability Co-Design Approach for High Voltage LDMOS Devices
      • Infineon Technology, Munich and Kuching, Oct. 2020
      • NXP, Nijmegen, Netherlands (June 29th, 2018)
      • Semiconductor Complex Limited (SCL), Department of Space, July 2nd 2015
      • ANURAG, DRDO, Feb 2017
      • LRDE, DRDO, Feb 2017
  6. On Chip ESD Design: Why EDA Based Approach is Becoming Important?”, Keynote talk at Cadence India Design Center, Dec 11th 2015
  7.  “On-Chip ESD Devices and Circuits: Essentials and Research Opportunities
      • 3rd India ESD Workshop, Feb 25th, 2019
      • 2nd India ESD Workshop, March 17th, 2017
      • 1st India ESD Workshop, Feb 26th, 2016
      • IIT Gandhinagar, Dec. 31st 2015
      • Semiconductor Complex Limited (SCL), Department of Space, July 1st 2015
      • EE Department, IIT Madras, July 2014
      • Texas Instruments Bangalore, India, April 2014
      • CRL Bangalore, Feb. 2014
      • Fifth Electrical Sciences Symposium, IISc Bangalore, Feb. 2014
  8.  “ESD Design Essentials”, Bangalore, 8th and 9th Jan. 2015
      • ESD Device Physics
      • On-Chip ESD (Circuit) Design
      • CDM Phenomena and Protection Design
      • Latch-up
  9. How Experimental and Computational Probes Enabled Development of (India’s First) GaN Based Power Transistor and Diode Technologies
      • The Third Indian Materials Conclave and the 32nd Annual General Meeting of MRSI, Dec 2021
      • IWPSD, IIT Delhi, Dec 2021
      • IEEE ICEE, IIT Delhi, Nov. 2020
  10. “Should India Buy a Fab” / “India’s Race for Nanomanufacturing”
      • Bangalore Nano, March 2022
      • World Congress on Micro Nano Manufacturing, IIT Bombay, Sep. 2021
      • VAIBHAV Summit, Oct. 2020
  11. How Wide Bandgap Semiconductors Like GaN Can Transform Power Electronics Industry?”, Keynote Talk, Cyient Power Electronics Conference, Oct. 2021
  12. “THz Electronics Opportunities and R&D Challenges”, Invited talk in the International Workshop on THz Technology, IIT Delhi, Sep 21st 2019
  13.  “Towards the end of Moore’s Law: Options and Challenges Beyond Advanced FinFET Technologies to Sustain CMOS ULSI”, Tutorial talk at IWPSD – Dec 2019
  14. “Defect Assisted Atomic Orbital Overlap Engineering for Metal – 2D Material’s Contacts & Record High Performance Transistors”
      • Invited talk at IWPSD – Dec 2019
      • IEEE ICEE, IIT Delhi, Nov. 2020
  15. “ESD Reliability and Physics of Carbon Electronics”, International ESD Workshop, USA, 1st April, 2019
  16. ESD Robust LDMOS Design Essentials” Online webinar organized by ESD Association USA, telecasted globally in Nov. 2014.
  17.  “IC and System Design for Electrostatic Discharge Protection”, IEEE INDICON, Dec. 2013
  18. Drain extended MOS device design and reliability challenges” IWPSD Dec. 2013
  19. A Review on the ESD Robustness of Drain Extended MOS Devices” International ESD workshop, May 20, 2013, Warrenton, VA, USA
  20. 3D TCAD Based approach for ESD failure analysis“, Infineon Technologies, AG, Munich (Germany), June 2010.
  21. Reliability aware I/O design for sub 45nm node CMOS technology” IWPSD-2009, 18th Dec, 2009.
  22. Benchmarking the device performance at sub 22 nm node technologies using an SoC framework“, IWSG-2009, 3rd Dec 2009.
  23. 3D filament behavior of various HV DeMOS devices under ESD condition” University of California (SB), USA, 4th Sep, 2009.
  24. Filament behavior of various DeMOS devices“, Technical University of Vienna, Austria, 8th Oct 2008.
  25. ESD optimization of DeMOS devices“, Infineon Technologies, AG, Munich (Germany), 6th Oct 2008.
  26. Mixed signal and hot carrier performance of various DeMOS devices” Infineon Technologies, AG, Munich (Germany), 3rd May 2008.

Patents

Granted Patents (#1 – #30 are granted in US, #31 granted in India, #1 – #20 granted in two or more than two countries)

  1. Rajesh Thakkar, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, “Operational Amplifier Having Improved Slew Rate ” United States Patent (03-01-2012) 8,089,314 (Also filed/granted in other countries, India: 542/MUM/2010, European Patent: EP2543141; Chinese Patent: CN102474230; and PCT: WO2011107824)
  2. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “Nonvolatile floating gate analog memory cell”, United States Patent (07-05-2013) 8,436,413 (Also filed/granted in other countries, Indian Patent No 258773; and PCT: WO2010046922.)
  3. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei,” Semiconductor devices with trench isolations”, United States Patent (17-01-2012) 8,097,930 (Also granted in Germany, Patent No: DE102009034405)
  4. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-effect device and manufacturing method thereof”, United States Patent (15-01-2013) 8,354,710 (Also granted in Germany, Patent No: DE102009030086)
  5. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, Ramgopal Rao, Christian Russ, “Device and method for coupling first and second device portions”, United States Patent (04-06-2013) 8,455,947  (Also granted in Germany, Patent No: DE102010000355)
  6. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain extended field effect transistors and methods of formation thereof”, United States Patent (17-09-2013) 8,536,648  (Also granted in Germany, Patent No: DE102012100767)
  7. Mayank Shrivastava and Harald Gossner, “Drain extended MOS device for Bulk FinFET technology”, United States Patent (14-01-2014) 8,629,420 (Also granted in Germany, Patent No: DE102013106152; Taiwan, Patent No: TW201411844 and in China, Patent No: CN103531633)
  8. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Semiconductor devices and methods for manufacturing a semiconductor device”, United States Patent (04-02-2014) 8,643,090 (Also granted in Germany, Patent No: DE102010016000)
  9. Mayank Shrivastava, Christian Russ, Harald Gossner, “Low voltage ESD clamping using high voltage devices”, United States Patent (18-02-2014) 8,654,491 (Also granted in Germany, Patent No: DE102013103076; and in China, Patent No: CN107424988)
  10. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, “High voltage semiconductor devices”, United States Patent (04-03-2014) 8,664,720 (Also granted in Germany, Patent No: DE102011050958)
  11. Mayank Shrivastava, Christian Russ, Harald Gossner, “Selective current pumping to enhance low-voltage ESD clamping using high voltage devices”, United States Patent (25-03-2014) 8,681,461 (Also granted in Germany, Patent No: DE102013103076 and in China, Patent No: CN103367357)
  12. Mayank Shrivastava and Harald Gossner, “Silicon controlled rectifier (SCR) device for bulk FinFET technology”, United States Patent (22-07-2014) 8,785,968 (Also granted in Taiwan, Patent No: TW201423957)
  13. Mayank Shrivastava, Christian Russ and Harald Gossner, “Tunable Fin-SCR for Robust ESD Protection”, United States Patent (24-02-2015) 8,963,201.
  14. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-Effect Device and Manufacturing Method Thereof”, United States Patent (19-05-2015) 9,035,375 (Also granted in Germany, Patent No: DE102009030086)
  15. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain Extended Field Effect Transistors and Methods of Formation Thereof”, United States Patent (21-07-2015) 9,087,892 (Also granted in Germany, Patent No: DE102012100767).
  16. Mayank Shrivastava and Christian Russ, “Semiconductor devices and arrangements for electrostatic (ESD) protection”, United States Patent (31-05-2016) 9,356,013.
  17. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, Ramgopal Rao, “Methods for manufacturing a semiconductor device”, United States Patent (14-06-2016) 9,368,573 (Also granted in Germany, Patent No: DE102010016000)
  18. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-effect device and manufacturing method thereof”, United States Patent (26-07-2016) 9,401,352 (Also granted in Germany, Patent No: DE102009030086)
  19. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, “High voltage semiconductor devices”, United States Patent (27-09-2016) 9,455,275. (Also granted in Germany, Patent No: DE102011050958).
  20. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain extended field effect transistors and methods of formation thereof”, United States Patent (09-05-2017) 9,647,069. (Also granted in Germany, Patent No: DE102012100767)
  21. Mayank Shrivastava, Christian Russ and Harald Gossner, “Tunable FIN-SCR for Robust ESD Protection”, United States Patent (28-03-2017) 9,608,098.
  22. Mayank Shrivastava and Christian Russ, “Semiconductor Devices And Arrangements Including Dummy Gates For Electrostatic Discharge Protection”, United States Patent No: (14-03-2017) 9,595,516.
  23. Mayank Shrivastava, Milova Paul, Christian Russ and Harald Gossner, “Non-planar Electrostatic Discharge (ESD) Protection Devices With Nano Heat Sinks”, US Patent No (11-06-2019): 10,319,662 (Indian Patent, Application No 201741003773, Filed on 1st Feb. 2017)
  24. Mayank Shrivastava, Milova Paul, Christian Russ and Harald Gossner, “Low Trigger and Holding Voltage Silicon Controlled Rectifier (SCR) For Non-Planar Technologies”, US Patent No (19-02-2019): 10,211,200 (Indian Patent, Application No 201741003772, Filed on 1st Feb. 2017)
  25. Mayank Shrivastava, Milova Paul and Harald Gossner, “Electrostatic Discharge (ESD) Protection Devices For ESD Robustness, Latch-Up and Hot Carrier Immunity”, US Patent No (19-11-2019): 10,483,258 (Indian Patent No. 376841)
  26. Milova Paul, Mayank Shrivastava, Sampath Kumar, Christian Russ and Harald Gossner, “Dual Fin Silicon Controlled Rectifier (SCR) Electrostatic Discharge (ESD) Protection Device”, US Patent No (21-04-2020): 10,629,586 (Indian Patent, Application No 201741003771, Filed on 1st Feb. 2017)
  27. Mayank Shrivastava, Recess Gate Superjunction High-electron-mobility transistor (HEMT)”, US Patent No (02-02-2020): 10,553,712 (Indian Patent Application 201741024695, July 2017.)
  28. Mayank Shrivastava, Milova Paul and Harald Gossner, “FinFET SCR With SCR Implant Under Anode And Cathode Junctions”, US Patent No (04-02-2020): 10,535,762, (Indian Patent, Application No 201741006746, Filed on 25th Feb. 2017)
  29. Mayank Shrivastava, Sayak Dutta Gupta, Ankit Soni, Srinivasan Raghavan and Navakanta Bhat, “Enhancement Mode High Electron Mobility Transistor (HEMT)”, US Patent No (17-11-2020): 10,840,348 (Indian Patent Application 201741030570, August 2017)
  30. Mayank Shrivastava and Vipin Joshi, “Doping and Trap Profile Engineering in GaN Buffer To Maximize AlGaN/GaN HEMT Epi Stack Breakdown Voltage”, US Patent No (08-06-2021):11,031,493 (Indian Patent Application 201841020899, Filled on June 5th 2019)
  31. Rohit Soman, Ankit Soni, Mayank Shrivastava, S. Raghavan and Navakanta Bhat “High Electron Mobility Transistor (HEMT) with Resurf Junction”, US Patent Application No: US20200227543 A1  (Indian Patent No: 310947)

 

Filed, but not granted:

  1. Mayank Shrivastava, “Drain extended Tunnel FET”, US Patent Pending, Application No: US2021119044 (A1), Filed on: 23-Feb-17 (Indian Patent Application No: 201641006497, Filed on Feb 26th 2016 ) 
  2. Adil Meersha, Mamta Khaneja and Mayank Shrivastava, A Method of Depositing Gate Dielectric on a 2D Material, Indian Patent Application: 202111057162, Dec. 8th, 2021.
  3. Adil Meersha, Mohan Lal and Mayank Shrivastava, Multilayer Graphene Contact for Monolayer Graphene Channel, Indian Patent Application: 202111057161, Dec. 8th, 2021.
  4. Adil Meersha, Jaswant Singh Rawat and Mayank Shrivastava, Method to Selectively Etch h-BN, Indian Patent Application: 20111057160, Dec. 8th, 2021.
  5. Adil Meersha, Prashant Kumar and Mayank Shrivastava, Graphene Transistor with Defected Graphene Layer, Indian Patent Application: 20111057163, Dec. 8th, 2021.
  6. Monishmurali M and Mayank Shrivastava, “Fin-Based SCR Architectures Having Distributed Current Configuration and Enhanced ESD Protection”, Indian Patent Application No: 202041011502, Filing Date: March 17th, 2020
  7. Ankit Soni and Mayank Shrivastava, “Novel Drain Connected Field Plate HEMT Designs having Improved Performance”, Indian Patent Application No: 202041010165, Filing Date: 9th March 2020
  8. Ankit Soni and Mayank Shrivastava, “High Electron Mobility Transistor with improved performance and linearity”, Indian Patent Application No: 201941052639 (Filed on 29th December, 2019)
  9. Mayank Shrivastava, “A Flexible, Adaptive Neuromorphic Synaptic Chip” Indian Patent Application No: 201941028863, Filed on 17th July 2019.
  10. Ansh, Hemanjaneyulu Kuruva and Mayank Shrivastava, “Methods of Manufacturing 2-Dimentional Semiconductor Transistors”, Indian Patent Application No. 201741033081, September 2017
  11. S. Kranthi, K. Hemanjaneyulu, and Mayank Shrivastava, “A Field Effect Transistor (FET) with Improved Failure Threshold”, Indian Patent Application No. 201741025123, July 2017
  12. Mayank Shrivastava and Kuruva Hemanjaneyulu “Fin enabled area scaled tunnel field Effect transistor”, Patent Application No: 2625/CHE/2015, Filed on May 26th 2015
  13. Mayank Shrivastava, “Miniaturized, High Power Density Power Electronic System on a Chip”, Patent Application No: 1355/CHE/2015, Filed on March 19th 2015

List of Publications

Over 150 publications in IEEE journals and peer reviewed conferences of high repute. 33 publications in the IEEE International Electron Devices Meeting (IEDM) & the IEEE International Reliability Physics Symposium (IRPS), which are the two most prestigious conferences for Electron Devices.

Books, Book chapters and Technical Briefs

  1. Chapter titled “Towards Drain extended FinFETs for SoC applications” in book “Toward Quantum FinFET”, edited by Weihua Han and Zhiming M. Wang, Springer, Dec. 2013, ISBN 978-3-319-02021-1.
  1. Mayank Shrivastava and V. Ramgopal Rao, “Tunnel Field Effect Transistors”, Present, Past and Future, Technical Brief appeared in the IEEE EDS Newsletters, July 2016 (Cover page article).

Peer Reviewed International Journals

  1. Ankit Soni and Mayank Shrivastava, “Implications of Various Charge Sources in AlGaN/GaN Epi-Stack on the Drain & Gate Connected Field Plate Design in HEMTs”, Accepted to appear in IEEE Access
  2. Jeevesh Kumar, Utpreksh Patbhaje and Mayank Shrivastava, “Role of Channel Inversion in Ambient Degradation of Phosphorene FETs”, IEEE Transactions on Electron Devices, Volume: 69, Issue: 6, June 2022. DOI: 10.1109/TED.2022.3171504
  3. N. K. Kranthi, James Di Sarro, Krishna Rajagopal, Hans Kunz, Rajkumar Sankaralingam, Gianluca Boselli, and Mayank Shrivastava, “Unique Rise Time Sensitivity Leading to Air Discharge System Level ESD Failures in Bi-Directional High Voltage SCRs”, Published (March 28th 2022) IEEE Transactions on Electron Devices, DOI: 10.1109/TED.2022.3159281
  4. Kuruva Hemanjaneyulu, Adil Meersha, Jeevesh Kumar and Mayank Shrivastava, “Unveiling Unintentional Fluorine Doping in TMDs During the Reactive Ion Etching: Root Cause Analysis, Physical Insights, and Solution”, Published (March 9th 2022) IEEE Transactions on Electron Devices, DOI: 10.1109/TED.2022.3152459
  5. Hemanjaneyulu Kuruva, Jeevesh Kumar and Mayank Shrivastava, “Gaps in the Y-Function Method For Contact Resistance Extraction in 2D Few-Layer Transition Metal Dichalcogenide Back-Gated FETs”, Published (7th Feb 2022) IEEE Electron Device Letters. DOI: 10.1109/LED.2022.3149410
  6. Aakanksha Mishra, Mayank Shrivastava and Ankur Gupta, “The Root Cause Behind a Peculiar Dual-Mode ON-State Breakdown in High Voltage LDMOS”, Published (23rd Feb 2022) in IEEE Transactions on Electron Devices. DOI: 10.1109/TED.2022.3149236
  7. Jeevesh Kumar, Adil Meersha, Harsha Balakrishnan Variar, Abhishek Mishra and Mayank Shrivastava, “Carbon Vacancy Assisted Contact Resistance Engineering in Graphene FETs”, Published (28th Feb 2022) in IEEE Transactions on Electron Devices. DOI: 10.1109/TED.2022.3151033
  8. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri and Mayank Shrivastava, “Unique Gate Bias Dependence of Dynamic ON Resistance in MIS-gated AlGaN/GaN HEMTs & Its Dependence on Gate Control over the 2-DEG”, IEEE Transactions on Electron Devices, Volume: 69, Issue: 3, March 2022. DOI: 10.1109/TED.2022.3144378
  9. N. S. Kranthi, Gianluca Boselli and Mayank Shrivastava, “HV-LDMOS Device Engineering Insights for Moving Current Filament to Enhance ESD Robustness”, IEEE Transactions on Electron Devices, Volume: 69, Issue: 3, March 2022. DOI: 10.1109/TED.2022.3143073
  10. Jeevesh Kumar and Mayank Shrivastava, “First-Principles Molecular Dynamics Insight into Atomic Level Degradation Pathway of Phosphorene”, ACS Omega, Volume: 7, Issue: 1, 696–704, January 2022. DIO: https://doi.org/10.1021/acsomega.1c05353
  11. Ansh and Mayank Shrivastava, “Superior Resistance Switching in Monolayer MoS2 Channel Based Gated Binary Resistive RAM via Gate-Bias Dependence and a Unique Forming Process”, Journal of Physics D: Applied Physics, Volume 55, Number 8, Nov. 2021.
  12. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri and Mayank Shrivastava, “Part I: Physical Insights into Dynamic RON Behavior and a Unique Time Dependent Critical Stress Voltage in AlGaN/GaN HEMTs” IEEE Transaction of Electron Devices, Volume: 68, Issue: 11, Nov. 2021. DOI: 10.1109/TED.2021.3109847
  13. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri and Mayank Shrivastava, “Novel Surface Passivation Scheme by Using p-Type AlTiO to Mitigate Dynamic ON Resistance Behavior in AlGaN/GaN HEMTs – Part II”, IEEE Transaction of Electron Devices, Volume: 68, Issue: 11, Nov. 2021. DOI: 10.1109/TED.2021.3064531
  14. Mayank Shrivastava and V. Ramgopal Rao, “A Roadmap for Disruptive Applications & Heterogeneous Integration using 2-Dimensional Materials: State-of-the-Art and Technological Challenges”, ACS Nano Letters, 21, 15, 6359–6381, August 2021. DOI: https://doi.org/10.1021/acs.nanolett.1c00729
  15. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri and Mayank Shrivastava, “Observations Regarding Deep-Level States Causing p-Type Doping in AlTiO Gate & Positive Threshold Voltage Shift in AlGaN/GaN High Electron Mobility Transistors” Journal of Applied Physics 130, 015701 (2021). DOI: https://doi.org/10.1063/5.0053982
  16. Rajarshi Roy Chaudhuri, Vipin. Joshi, Sayak Dutta Gupta and Mayank Shrivastava, “On the Channel Hot-Electron’s Interaction with C-doped GaN Buffer and Resultant Gate Degradation in AlGaN/GaN HEMTs,” IEEE Transactions on Electron Devices, Volume: 68, Issue: 10, Oct. 2021. DOI: 10.1109/TED.2021.3102469
  17. N. K. Kranthi, James Di Sarro, Rajkumar Sankaralingam, Gianluca Boselli and Mayank Shrivastava, “System-Level IEC ESD failures in High Voltage DeNMOS-SCR: Physical Insights and Design Guidelines”, IEEE Transactions on Electron Devices, Volume: 68, Issue: 9, Sept. 2021. DOI: 10.1109/TED.2021.3100810
  18. Ankit Soni and Mayank Shrivastava, “Interplay of Various Charge Sources in AlGaN/GaN Epi-Stack Governing HEMT Breakdown”, IEEE Transaction of Electron Devices, Volume: 68, Issue: 5, May 2021. DOI: 10.1109/TED.2021.3068079
  19. Abhishek Mishra, Adil Meersha, N.K. Kranthi, Jeevesh Kumar, N.S. Veenadhari Bellamkonda, Harsha B. Variar and Mayank Shrivastava, “Unified Mechanism for Graphene FET’s Electro-Thermal Breakdown & its Implications on Safe Operating Limits”, IEEE Transaction of Electron Devices, Volume: 68, Issue: 5, May 2021. DOI: 10.1109/TED.2021.3068081
  20. Ankit Soni and Mayank Shrivastava, “Design Guidelines for Recessed Schottky Barrier AlN/GaN Diode for THz Applications”, IEEE Transaction of Electron Devices, Volume: 68, Issue: 5, May 2021, DOI: 10.1109/TED.2021.3064541
  21. Jeevesh Kumar, Ansh, Mayank Shrivastava, “Introduction of Near to Far Infrared Range Direct Band Gaps in Graphene: A First Principle Insight”, ACS Omega 2021, Vol. 6, Issue: 8, 5619–5626, Feb 2021. DOI: https://doi.org/10.1021/acsomega.0c06058
  22. Vipin Joshi, Sayak Dutta Gupta, Rajarshi Roy Chaudhuri and Mayank Shrivastava “Part-I: Physical Insights into the Impact of Surface Traps on Breakdown Characteristics of AlGaN/GaN HEMTs”, IEEE Transaction on Electron Device, Volume: 68, Issue: 1, Pages: 72-79, Jan 2021. DOI: 10.1109/TED.2020.3034561
  23. Vipin Joshi, Sayak Dutta Gupta, Rajarshi Roy Chaudhuri and Mayank Shrivastava “Interplay between Surface and Buffer Traps in Governing Breakdown Characteristics of AlGaN/GaN HEMTs – Part II”, IEEE Transaction on Electron Device, Volume: 68, Issue: 1, Pages: 80-87, Jan 2021. DOI: 10.1109/TED.2020.3034562
  24. Jeevesh Kumar, Ansh and Mayank Shrivastava, “Stone-Wales Defect Vacancy Assisted Enhanced Atomic Orbital Interactions Between Graphene & Ambient Gases: A First Principles Insight”, ACS Omega, Volume: 5, Issue: 48, Pages: 31281-31288, Dec 2020. DOI: https://doi.org/10.1021/acsomega.0c04729
  25. Bhawani Shankar, Ankit Soni, Srinivasan Raghavan and Mayank Shrivastava, “Trap Assisted and Stress Induced Safe Operating Area Limits of AlGaN/GaN HEMTs”, IEEE Transaction on Device and Materials reliability, Volume: 20, Issue: 4, Pages: 767-774, Dec 2020. DOI: 10.1109/TDMR.2020.3033522
  26. Ansh, Jeevesh Kumar, Gaurav Sheoran and Mayank Shrivastava, “Electrothermal Transport Induced Material Re-Configuration and Performance Degradation of CVD-Grown Monolayer MoS2 Transistors”, Nature (npj) 2D Materials and Applications, 4 (1), 1-11, Nov. 2020. DOI: https://doi.org/10.1038/s41699-020-00171-3
  27. Ankit Soni and Mayank Shrivastava, “Design Guidelines and Performance Trade-offs in Recessed AlGaN/GaN Schottky Barrier Diodes”, IEEE Transactions of Electron Devices, Volume: 67, Issue: 11, Pages:4834-4841, Nov 2020. DOI: 10.1109/TED.2020.3024354
  28. B. Sampath Kumar, Ajay Singh, Milova Paul, Jhnanesh Somayaji, Harald Gossner and Mayank Shrivastava, “Device, Circuit, and Reliability Assessment of Drain-Extended FinFETs for Sub-14 nm System on Chip Applications”, Transactions on Electron Devices, Volume: 67, Issue: 11, Pages:4728-4735, Nov 2020. DOI: 10.1109/TED.2020.3020904
  29. Rajat Sinha, Prasenjit Bhattacharya, Sanjiv Sambandan and Mayank Shrivastava, “Nano-second timescale drain voltage induced electrical instabilities in hydrogenated amorphous silicon thin film transistors”, Japanese Journal of Applied Physics , Volume: 59, Issue: 7, Pages:074004, July 2020. DOI: 10.35848/1347-4065/
  30. Bhawani Shankar, Ankit Soni, Sayak Dutta Gupta, Swati Shikha, Sandeep Singh, Srinivasan Raghavan and Mayank Shrivastava, “Time Dependent Shift in SOA boundary and Early Breakdown of Epi-Stack in AlGaN/ GaN HEMTs Under Fast Cyclic Transient Stress”, IEEE Transactions on Device and Material Reliability, Volume: 20, Issue: 3, Pages:562-569, July 2020. DOI: 10.1109/TDMR.2020.3007128
  31. Milova Paul, Sampath B, Harald Gossner and Mayank Shrivastava, “Engineering Schemes for Bulk FinFET to Simultaneously Improve ESD/Latch-Up Behavior and Hot Carrier Reliability”, IEEE Transaction of Electron Devices, Volume: 67, Issue: 7, Pages:2745-2751, June 2020. DOI: 10.1109/TED.2020.2997757
  32. B. Sampath Kumar, Milova Paul, Harald Gossner and Mayank Shrivastava, “Physical Insights into the ESD Behavior of Drain Extended FinFETs (DeFinFETs) and Unique Current Filament Dynamics”, IEEE Transaction of Electron Devices, Volume: 67, Issue: 7, July 2020. DOI: 10.1109/TED.2020.2994170
  33. Andrew Naclerio Dmitri, N Zakharov, Jeevesh Kumar, Bridget R. Rogers, Cary L. Pint, Mayank Shrivastava and Piran R. Kidambi, “Visualizing Oxidation Mechanisms in Few-Layered Black Phosphorus via in-situ Transmission Electron Microscopy”, ACS Appl. Mater. Interfaces 2020, DOI: 10.1021/acsami.9b21116
  34. Bhawani Shankar, Ankit Soni and Mayank Shrivastava, “Electro-Thermo-Mechanical Reliability of Recessed Barrier AlGaN/GaN Schottky Diodes Under Pulse Switching Conditions”, IEEE Transaction of Electron Devices, Volume: 67, Issue:5, May 2020, pp: 2044-2051. DOI: 10.1109/TED.2020.2981568.
  35. Ankit Soni, Ajay Singh and Mayank Shrivastava, “Novel Drain Connected Field Plate GaN HEMT Designs for Improved VBD − RON Trade-off and RF PA Performance”, IEEE Transaction of Electron Devices, Volume: 67, Issue:4, APRIL 2020, pp: 1718-1725. DOI: 10.1109/TED.2020.2976636
  36. Bhawani Shankar, Srinivasan Raghavan and Mayank Shrivastava, “Distinct Failure Modes of AlGaN/GaN HEMTs under ESD Conditions” IEEE Transactions on Electron Devices, Volume: 67, Issue: 4, April 2020, pp: 1567 – 1574. DOI: 10.1109/TED.2020.2974508
  37. Ansh, Jeevesh Kumar, Gaurav Sheoran, Harsha Variar, Ravikesh Mishra, Hemanjaneyulu Kuruva, Adil Meersha, Abhishek Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Chalcogen Assisted Enhanced Atomic Orbital Interaction at TMDs–Metal Interface & Sulfur Passivation For Overall Performance Boost of 2D TMD FETs” IEEE Transactions on Electron Devices, Volume: 67, Issue:2, Feb. 2020, pp: 717-724. DOI: 10.1109/TED.2019.2958338.
  38. Ansh, Jeevesh. Kumar, Gaurav Sheoran, Ravikesh Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Selective Electron or Hole Conduction in Tungsten Diselenide (WSe2) Field Effect Transistors by Sulfur Assisted Metal Induced Gap State Engineering,” IEEE Transactions on Electron Devices, Volume: 67, Issue:1, Jan. 2020, pp: 383-388. DOI: 10.1109/TED.2019.2956781.
  39. M. Paul, B. Sampath Kumar, K. Karmel Nagothu, P. Singhal, H. Gossner and Mayank Shrivastava, “Drain-Extended FinFET With Embedded SCR (DeFinFET-SCR) for High-Voltage ESD Protection and Self-Protected Designs,” in IEEE Transactions on Electron Devices, vol. 66, no. 12, pp. 5072-5079, Dec. 2019. DOI: 10.1109/TED.2019.2949126.
  40. Prasenjit Bhattacharya, Rajat Sinha, Bikash Kumar Thakur, Virendra Parab, Mayank Shrivastava, Sanjiv Sambandan, “Adaptive Dielectric Thin Film Transistors-A Self-Configuring Device for Low Power Electrostatic Discharge Protection”, IEEE Electron Device Letters, Volume: 41, Issue: 1, Jan. 2020. DOI: 10.1109/LED.2019.2956838.
  41. Ankit Soni and Mayank Shrivastava, “Computational Modelling Based Device Design for Improved mmWave Performance and Linearity of GaN HEMTs,” IEEE Journal of the Electron Devices Society, Volume: 8, Issue:1, pp: 33-41, Jan 2020, DOI: 10.1109/JEDS.2019.2958915
  42. Rajat Sinha, Prasenjit Bhattacharya, Sanjiv Sambandan, and Mayank Shrivastava, “Nano-second timescale high-field phase transition in hydrogenated amorphous silicon.” Journal of Applied Physics 126, no. 13 (2019): 135706.
  43. Bhawani Shankar and Mayank Shrivastava, “Safe Operating Area of Polarization Super Junction GaN HEMTs & Diodes”, IEEE Transactions on Electron Devices, Volume: 66, Issue:9, Page(s): 3756-3763, September 2019, DOI: 10.1109/TED.2019.2926781.
  44. Ankit Soni, Swati Shikha and Mayank Shrivastava, “On the Role of Interface States in AlGaN/GaN Schottky Recessed Diodes: Physical Insights, Performance Tradeoff, and Engineering Guidelines”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 6, June 2019. DOI: 10.1109/TED.2019.2912783.
  45. Hemanjaneyulu Kuruva, Jeevesh Kumar and Mayank Shrivastava, “MoS2 Doping using Potassium Iodide for Reliable Contacts and Efficient FET Operation”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 7, July 2019, Page(s): 3224 – 3228. DOI: 10.1109/TED.2019.2916716.
  46. Sayak Dutta Gupta, Ankit Soni, Rudrarup Sengupta, Heena Khand, Bhawani Shankar, Nagboopathy Mohan, Srinivasan Raghavan, Navakanta Bhat, and Mayank Shrivastava, “Positive Threshold Voltage Shift in AlGaN/GaN HEMTs & E-mode Operation by AlxTi1-xO based Gate Stack Engineering”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 6, June 2019, Page(s): 2544 – 2550. DOI: 10.1109/TED.2019.2908960.
  47. Rajat Sinha, Prasenjit Bhattacharya, Tim Iben, Sanjeev Sambandan and Mayank Shrivastava, “ESD Reliability Study of a-Si:H Thin film Transistor Technology: Physical Insights and Technological Implications”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 6, June 2019. DOI: 10.1109/TED.2019.2913040.
  48. Bhawani Shankar, Rudrarup Sengupta, Sayak Dutta Gupta, Ankit Soni, Srinivasan Raghavan and Mayank Shrivastava, “ESD Behavior of AlGaN/GaN Schottky Diodes”, IEEE Transactions on Device and Materials Reliability, Volume: 19, Issue: 2, June 2019, Page(s): 437 – 444. DOI: 10.1109/TDMR.2019.2916846 (Invited Paper)
  49. Bhawani Shankar, Ankit Soni, Hareesh Chandrasekar, Srinivasan Raghavan and Mayank Shrivastava, “First Observations on the Trap Assisted Avalanche Instability and Safe Operating Area Concerns in AlGaN/GaN HEMTs”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 8, Aug. 2019, Page(s): 3433 – 3440. DOI: 10.1109/TED.2019.2919491.
  50. Bhawani Shankar and Mayank Shrivastava, “Unique ESD Behavior of AlGaN/GaN HEMTs”, IEEE Transactions on Device and Materials Reliability, Volume: 19, Issue: 2, June 2019, Page(s): 437 – 444. DOI: 10.1109/TDMR.2019.2916846.
  51. Nagothu Karmel Kranthi, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “ESD Behavior of Large Area CVD Graphene Transistors: Physical Insights and Technology Limitations”, IEEE Transactions on Electron Devices, Vol, 66, Issue: 1, Pages: 743 – 751, Jan. 2019. (DOI: 10.1109/TED.2018.2877693)
  52. Vipin Joshi, Shree Prakash Tiwari, and Mayank Shrivastava, “Part-I: Physical insight into breakdown voltage improvement with Carbon doping in AlGaN/GaN HEMTs”, IEEE Transactions on Electron Devices, Vol., 66, Issue: 1, Pages: 561 – 569, Jan. 2019. DOI: 10.1109/TED.2018.2878770
  53. Vipin Joshi, Shree Prakash Tiwari, and Mayank Shrivastava, ” Part II: Proposals to Independently Engineer Donor and Acceptor Trap Concentrations in GaN Buffer For Ultra High Breakdown AlGaN/GaN HEMTs”, IEEE Transactions on Electron Devices, Vol., 66, Issue: 1, Pages: 570 – 577, Jan. 2019. (DOI: 10.1109/TED.2018.2878787)
  54. Milova Paul, B. Sampath Kumar, Christian Russ, Harald Gossner, Mayank Shrivastava, “Challenges & Physical Insights into the Design of Fin Based SCRs and a Novel Fin-SCR for Efficient On-Chip ESD Protection”, IEEE Transactions of Electron Devices, Vol, 65, Issue: 11, Pages: 4755 – 4763, Nov. 2018. (DOI: 10.1109/TED.2018.2869630)
  55. Milova Paul, Christian Russ, B Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Physics of Current Filamentation in ggNMOS Devices Under ESD Condition Revisited “, IEEE Transactions on Electron Devices, Vol, 65 , Issue: 7, pp. 2981 – 2989, July 2018. (DOI: 10.1109/TED.2018.2835831)
  56. Abhishek Mishra, Adil Meersha, Srinivasan Raghavan and Mayank Shrivastava, “Observing Non-equilibrium State of Transport through Graphene Channel at the Nano-Second Time Scale”, Applied Physics Letters, Vol. 111, Issue: 26, Pages: 263101-6, Dec. 2018. (DOI: 10.1063/1.5006258)
  57. B Sampath Kumar and Mayank Shrivastava, “Part I: On the Unification of Physics of Quasi-Saturation in LDMOS Devices”, IEEE Transactions on Electron Devices, Vol. 65, Issue: 1, Pages: 191-198, Jan. 2018. (DOI:10.1109/TED.2017.2777004)
  58. B Sampath Kumar and Mayank Shrivastava, “Part II: RF, ESD, HCI, SOA, and Self Heating Concerns in LDMOS Devices Versus Quasi Saturation”, IEEE Transactions on Electron Devices, Vol. 65, Issue: 1, Pages: 199-206, Jan. 2018. (DOI:10.1109/TED.2017.2732504)
  59. Abhishek Misra, Harald Gossner and Mayank Shrivastava, “ESD Behavior of MWCNT Interconnects – Part I: Observations and Insights”, IEEE Transactions on Device and Material Reliability, Vol. 17, Issue: 4, Pages: 600-607, Dec. 2017. (DOI:10.1109/TDMR.2017.2756924) (Invited Review Paper)
  60. Abhishek Misra and Mayank Shrivastava, “ESD Behavior of MWCNT Interconnects – Part II: Unique Current Conduction Mechanism”, IEEE Transactions on Device and Material Reliability, Vol. 17, Issue: 4, Pages: 608-615, Dec. 2017. (DOI:10.1109/TDMR.2017.2738701) (Invited Review Paper)
  61. Jhnanesh Somayaji, B.Sampath Kumar, M. S. Bhat, Mayank Shrivastava, “Performance and Reliability Codesign for Superjunction Drain Extended MOS Devices “, IEEE Transactions on Electron Devices, Vol, 64, Issue: 10, Pages: 4175 – 4183, Oct. 2017.  (DOI: 10.1109/TED.2017.2733043)
  62. Abhishek Mishra, Ravi Nandan, Srinivasan Raghavan and Mayank Shrivastava, ” Nano-second time resolved investigations on thermal implications of high-field transport through MWCNTs”, Applied Physics Letters, Vol. 110, Pages:  233111-6, May 2017. (https://doi.org/10.1063/1.4984282)
  63. Abhishek Mishra and Mayank Shrivastava, “Remote Joule Heating Assisted Carrier Transport in MWCNTs Probed at Nanosecond Time Scale”, Physical Chemistry Chemical Physics (PCCP) Journal of Royal Society of Chemistry, Vol. 18, Pages: 28932-28938, Jun 2016. (DOI:10.1039/C6CP04497B)
  64. Mayank Shrivastava, “Drain Extended Tunnel FET – A Novel High Voltage Device for Beyond FinFET System on Chip & Automotive Applications”, IEEE Transactions on Electron Devices, Vol. 64, Issue: 2, Pages: 481 – 487, Feb. 2017. (DOI:10.1109/TED.2016.2636920)
  65. Vipin Joshi, Ankit Soni, Shree Prakash Tiwari and Mayank Shrivastava, “A Comprehensive Computational Modeling Approach for AlGaN/GaN HEMTs”, IEEE Transactions on Nanotechnology, Vol. 15, Issue: 6, Pages: 947 – 955, Nov. 2016. (DOI:10.1109/TNANO.2016.2615645)
  66. Kranthi Nagothu and Mayank Shrivastava, “On the ESD Behavior of Tunnel FET Devices”, IEEE Transactions on Electron Devices, Vol. 64, Issue: 1, Pages: 28 – 36, Jan. 2017. (DOI:10.1109/TED.2016.2630079)
  67. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, Harald Gossner, and V. Ramgopal Rao, “On the Improved High-Frequency Linearity of Drain Extended MOS Devices”, IEEE Microwave and Wireless Components Letters, Vol. 26, Issue: 12, Pages: 999-1001, Dec. 2016. (DOI:10.1109/LMWC.2016.2623239)
  68. Peeyusha S. Swain, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “On the Geometrically Dependent Quasi-Saturation and gm Reduction in Advanced DeMOS Transistors”, IEEE Transactions on Electron Devices, Vol. 63, Issue: 4, Pages: 1621 1629, April 2016. (DOI:10.1109/TED.2016.2528282)
  69. Mayur Ghatge and Mayank Shrivastava, “Physical Insights On the Ambiguous Metal Graphene Interface and Proposal for Improved Contact Resistance”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 12, Pages: 4139- 4147, Dec 2015. (DOI:10.1109/TED.2015.2481507)
  70. Ketankumar H. Tailor, Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, and V. Ramgopal Rao, “Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain Extended PMOS Device”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 12, Pages: 4097- 4104, Dec 2015. (DOI:10.1109/TED.2015.2481899)
  71. Ketankumar H. Tailor, Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, and V. Ramgopal Rao, “Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device”, IEEE Transactions on Electron Devices, Vol. 62, Issue 12, Pages: 4105-4113, Dec 2015. (DOI:10.1109/TED.2015.2488683)
  72. Kuruva Hemanjaneyulu and Mayank Shrivastava, “Fin Enabled Area Scaled Tunnel FET”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 10, Pages: 3184- 3191, Oct. 2015. (DOI:10.1109/TED.2015.2469678)
  73. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Part II: A Fully Integrated RF PA in 28nm CMOS with Device Design for Optimized Performance and ESD Robustness”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 10, Pages: 3176-3183, Oct. 2015. (DOI:10.1109/TED.2015.2470109)
  74. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Part I: High Voltage MOS Device Design for Improved Static and RF Performance”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 10, Pages: 3168- 3175, Oct. 2015. (DOI:10.1109/TED.2015.2470117)
  75. Mayank Shrivastava, Neha Kulshrestha and Harald Gossner, “ESD Investigations of Multiwalled Carbon Nanotubes”, IEEE Transactions on Device and Material Reliability, Vol. 14, Issue: 1, Pages: 555 – 563, March, 2014. (DOI:10.1109/TDMR.2013.2288362)
  76. Peeyush Swain, Mayank Shrivastava, Harald Gossner, M. S. Baghini and V. Ramgopal Rao, “Device–Circuit Co-design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors”, IEEE Transactions on Electron Devices, Vol. 60, Issue: 11, Pages: 3827-3834, November, 2013. (DOI:10.1109/TED.2013.2283421)
  77. Anukool Rajoriya, Mayank Shrivastava, Harald Gossner, Thomas Schulz and V. Ramgopal Rao “Sub 0.5V Operation of Performance Driven Mobile Systems Based on Area Scaled Tunnel FET Devices”, IEEE Transactions on Electron Devices, Vol. 60, Issue: 8, Pages: 2626-2633, August, 2013. (DOI:10.1109/TED.2013.2270566)
  78. Mayank Shrivastava and Harald Gossner, “A Review on the ESD Reliability of Drain Extended MOS Devices”, IEEE Transactions on Device and Material Reliability, Vol. 12, Issue: 4, Pages: 615-625, December, 2012. (DOI:10.1109/TDMR.2012.2220358) (Invited Paper)
  79. Mayank Shrivastava, Harald Gossner and V. Ramgopal Rao, “A Novel Drain Extended FinFET Device for High Voltage High Speed Applications”, IEEE Electron Device Letters, Vol. 33, Issue: 10, Pages: 1432-1434, October, 2012. (DOI:10.1109/LED.2012.2206791)
  80. Mayank Shrivastava, Harald Gossner and Christian Russ, “A Novel Drain Extended NMOS Device with Spreading Filament under ESD Stress”, IEEE Electron Device Letters, Vol. 33, Issue: 9, Pages: 1294-1296,  September, 2012. (DOI:10.1109/LED.2012.2205553)
  81. Mayank Shrivastava, Manish Agrawal, Sunny Mahajan, Harald Gossner, Thomas Schulz, Dinesh Kumar Sharma, and V. Ramgopal Rao, “Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures”, IEEE Transactions on Electron Devices, Vol. 59, Issue: 5, Pages: 1353-1363, May, 2012. (DOI:10.1109/TED.2012.2188296)
  82. Mayank Shrivastava, Ruchit Mehta, Shashank Gupta, M. Shojaei Baghini, D. K. Sharma, Harald Gossner, T. Schulz, K. Arnim, W. Molzer, V. Ramgopal Rao, “Towards System On Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 6, Pages: 1597-1607, June, 2011. (DOI:10.1109/TED.2011.2123100)
  83. Ram Asra, Mayank Shrivastava, K. V. R. M. Murali, R. K. Pandey, Harald Gossner and V. Ramgopal Rao, “A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS-Comparable Performance”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 7, Pages: 1855-1863, July, 2011. (DOI:10.1109/TED.2011.2140322)
  84. Rajesh A. Thakker, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, and Mahesh B. Patil, ” A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs”, Microelectronics Journals, Vol. 42, Issue: 5, Pages: 758–765, May, 2011. (https://doi.org/10.1016/j.mejo.2011.01.010)
  85. Mayank Shrivastava, Ruchil Jain, M. Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “Solution towards the OFF state degradation in Drain extended MOS device”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 12,Pages:  3536-3539, December, 2010. (DOI:10.1109/TED.2010.2082549)
  86. Amitabh Chatterjee, Mayank Shrivastava, Harald Gossner, Sameer Pendharkar, Forrest Brewer, Charvaka Duvvury, ” An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device—Part I: Turn-On Behavior of the Parasitic Bipolar”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 2, Pages: 309 – 317, February, 2011. (DOI:10.1109/TED.2010.2093010)
  87. Amitabh Chatterjee, Mayank Shrivastava, Harald Gossner, Sameer Pendharkar, Forrest Brewer, Charvaka Duvvury, ” An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II(Two-Dimensional Study-Biasing & Comparison With NMOS)”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 2, Pages: 318 – 326, February, 2011. (DOI:10.1109/TED.2010.2093011)
  88. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Part I: On the Behavior of STI-Type DeNMOS Device under ESD Conditions”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 9, Pages: 2235 – 2242, September 2010. (DOI:10.1109/TED.2010.2055276)
  89. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 9, Pages: 2243 – 2250, September 2010. (DOI:10.1109/TED.2010.2055278)
  90. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “A novel bottom spacer FinFET structure for improved power-delay & short channel performance”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 6, Pages: 1287-1994, June 2010. (DOI:10.1109/TED.2010.2045686)
  91. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “PART I-“Mixed Signal Performance of Various High Voltage Drain Extended MOS devices” IEEE Transactions on Electron Devices, Vol. 57, Issue: 2, Pages: 448-457, Feb 2010. (DOI:10.1109/TED.2009.2036796)
  92. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “PART II-“A Novel scheme to optimize the mixed signal performance and hot carrier reliability of Drain Extended MOS devices” IEEE Transactions on Electron Devices, Vol. 57, Issue: 2, Pages: 458-465, Feb 2010. (DOI:10.1109/TED.2009.2036799)
  93. Mayank Shrivastava, Maryam Shojaei Baghini, A. Sachid, Dinesh Kumar Sharma, V. Ramgopal Rao, “A Novel and Robust Approach for Common Mode Feedback using IDDG FinFET”, IEEE Transactions on Electron Devices, Vol, 55, Issue: 11,Pages: 3274-3282, Nov 2008. (DOI:10.1109/TED.2008.2004475).

Peer Reviewed International IEEE Conferences with Proceedings (Available On IEEE Xplore)

  1. Jeevesh Kumar and Mayank Shrivastava, “Are Argon and Nitrogen Gases Really Inert to Graphene Devices”, to appear in the Proceedings of the 80th IEEE Device Research Conference (DRC), Columbus, Ohio, June 26-29, 2022
  2. Monish Murali, Nagothu Karmel Kranthi, Gianluca Boselli and Mayank Shrivastava, “Effect of Source & Drain Side Abutting on the Low Current Filamentation in LDMOS-SCR Devices”, Proceedings of 60th IEEE International Reliability Physics Symposium (IRPS), Dallas, USA, March 27th-31st, 2022.
  3. Monish Murali and Mayank Shrivastava, “A Novel High Voltage Drain Extended FinFET SCR for SoC Applications”, Proceedings of 59th IEEE International Reliability Physics Symposium (IRPS), USA, March 21-25, 2021. DOI: 10.1109/IRPS46558.2021.9405194
  4. Monish Murali and Mayank Shrivastava, “Peculiar Current Instabilities & Failure Mechanism in Vertically Stacked Nanosheet ggN-FET”, Proceedings of 59th IEEE International Reliability Physics Symposium (IRPS), USA, March 21-25, 2021. DOI: 10.1109/IRPS46558.2021.9405147
  5. Jhnanesh Somayaji B, Monishmurali, Ajay Singh, Kranthi N.K. and Mayank Shrivastava, “3D TCAD studies of Snapback Driven Failure in Punchthrough TVS Diodes under System Level ESD Stress Conditions”, Proceedings of 42nd EOSESD Symposium, September 2020, Sep. 13th – Sep. 18th, USA.
  6. Nagothu Karmel Kranthi, James Di Sarro, Rajkumar Sankaralingam, Gianluca Boselli and Mayank Shrivastava, “Insights into the System Level IEC ESD Failure in High Voltage DeNMOS-SCR for Automotive Applications”, Proceedings of 42nd EOSESD Symposium, September 2020, Sep. 13th – Sep. 18th, USA
  7. Jeevesh Kumar, Ansh, Hemanjaneyulu Kuruva and Mayank Shrivastava, “Defect Assisted Metal-TMDs Interface Engineering: A First Principle Insight”, 78th Device Research Conference (DRC), June 21st – 24th, 2020, USA. DOI: 10.1109/DRC50226.2020.9135158
  8. Rajat Sinha, Prasenjit Bhattacharya, Sanjiv Sambandan and Mayank Shrivastava, “Threshold voltage shift in a-Si:H Thin film transistors under ESD stress”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9128355
  9. Nagothu Karmel Kranthi, B. Sampath Kumar, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Design Insights to Address Low Current ESD Failure and Power Scalability Issues in High Voltage LDMOS-SCR Devices”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9129624
  10. Nagothu Karmel Kranthi, B. Sampath Kumar, Chirag Garg, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “How to Achieve Moving Current Filament in High Voltage LDMOS Devices: Physical Insights & Design Guidelines for Self-Protected Concepts”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9128332
  11. Monish Murali M, Milova Paul and Mayank Shrivastava, “Improved Turn-on Uniformity & Failure Current Density by n- & p-Tap Engineering in Fin Based SCRs”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9129356
  12. Ansh, Gaurav Sheoran, Jeevesh Kumar and Mayank Shrivastava, “First Insights into Electro-Thermal Stress Driven Time-Dependent Permanent Degradation & Failure of CVD Monolayer MoS2 Channel”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9129173
  13. Jeevesh Kumar, Asha Yadav, Anant Kumar Singh, Andrew Naclerio, Dmitri Zakharov, Piran Kidambi and Mayank Shrivastava, “Physical Insights into Phosphorene Transistor Degradation Under Exposure to Atmospheric Conditions and Electrical Stress”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9129123
  14. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri, Anant kr. Singh, Sirsha Guha and Mayank Shrivastava, “On the Root Cause of Dynamic ON Resistance Behavior in AlGaN/GaN HEMTs”, Proceedings of 58th IEEE International Reliability Physics Symposium (IRPS), Dallas, Texas, USA, April 2020. DOI: 10.1109/IRPS45951.2020.9128226
  15. Aakanksha Mishra, B. Sampath Kumar, Jhnanesh Somayaji, Mayank Shrivastava and Ankur Gupta, “Impact of Space Charge Modulation on Superjunction-LDMOS”, IEEE VLSI-TSA, Taiwan, April 2020. DOI: 10.1109/VLSI-TSA48913.2020.9203659
  16. Rajarshi Roy Chaudhuri, Sayak Dutta Gupta, Vipin Joshi and Mayank Shrivastava, “Interaction of Hot Electrons with Carbon Doped GaN Buffer in AlGaN/GaN HEMTs: Correlation with Lateral Electric Field and Device Failure”, Proceedings of 32nd IEEE International Symposium on Power Semiconductor Devices and ICs, Vienna, Austria, May 17-21, 2020. DOI: 10.1109/ISPSD46842.2020.9170160
  17. Jeevesh Kumar, Adil Meersha, Ansh and Mayank Shrivastava, “A First Principle Insight into Defect Assisted Contact Engineering at the Metal-Graphene and Metal-Phosphorene Interfaces”, 24th IEEE SISPAD, Italy, September 2019. DOI: 10.1109/SISPAD.2019.8870396
  18. Nagothu Karmel Kranthi, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Performance and Reliability Co-Design of LDMOS-SCR for Self-Protected High Voltage Applications on-Chip”, 31st IEEE Intl. Symposium on Power Semiconductor Devices & ICs, May 19-23, 2019. DOI: 10.1109/ISPSD.2019.8757641
  19. Nagothu Karmel Kranthi, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Current Filament Dynamics Under ESD Stress in High Voltage (Bidirectional) SCRs and Its Implications on Power Law Behavior”, 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019. DOI: 10.1109/IRPS.2019.8720484
  20. Abhishek Mishra, Adil Meersha, N. K. Kranthi, Kruti Trivedi, Harsha B. Variar, Veena Bellamkonda, Srinivasan Raghavan and Mayank Shrivastava, “First Demonstration and Physical Insights into Time-dependent Breakdown of Graphene Channel and Interconnects”, 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019. DOI: 10.1109/IRPS.2019.8720452
  21. Sayak Dutta Gupta, Vipin Joshi, Srinivasan Raghavan and Mayank Shrivastava, “UV-Assisted Probing of Deep-Level Interface Traps in GaN MISHEMTS and Its Role In Threshold Voltage & Gate Leakage Instabilities”, 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019. DOI: 10.1109/IRPS.2019.8720595
  22. Nagothu Karmel Kranthi, B. Sampath Kumar, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Physical Insights into the Low Current ESD Failure of LDMOS-SCR and Its Implication on Power Scalability”, 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019. DOI: 10.1109/IRPS.2019.8720580
  23. Bhawani Shankar, Ankit Soni, Sayak Dutta Gupta, Swati Shikha, Sandeep Singh, Srinivasan Raghavan and Mayank Shrivastava, “Time Dependent Early Breakdown of AlGaN/GaN Epi Stacks and Shift in SOA Boundary of HEMTs Under Fast Cyclic Transient Stress”, 64th IEEE International Electron Device Meeting (IEDM)– 2018, CA, USA, DOI: 10.1109/IEDM.2018.8614690
  24. Kuruva Hemanjaneyulu, Mamta Khaneja, Adil Meersha, Harsha B Variar and Mayank Shrivastava, “Comprehensive Computational Modelling Approach for Graphene FETs”, 4th IEEE ICEE, 2018. DOI: 10.1109/ICEE44586.2018.8937909
  25. B Sampath Kumar, Milova Paul, Harald Gossner and Mayank Shrivastava, “Physical Insights into the ESD Behavior of Drain extended FinFETs”, to appear in 40th EOSESD Symposium, Sep. 23rd to 28th 2018, Reno, NV, USA DOI: 10.23919/EOS/ESD.2018.8509695
  26. Bhawani Shankar, Rahul Singh, Rudrarup Sengupta, Heena Khand, Ankit Soni, Sayak D. Gupta, Srinivasan Raghavan and Mayank Shrivastava, “Trap Assisted Stress Induced ESD Reliability of GaN Schottky Diodes”, to appear in 40th EOSESD Symposium, Sep. 23rd to 28th 2018, Reno, NV, USA DOI: 10.23919/EOS/ESD.2018.8509745
  27. Bhawani Shankar, A. Soni, S. D. Gupta and Mayank Shrivastava, “Safe Operating Area (SOA) Reliability of Polarization Super Junction (PSJ) GaN FETs”, 56th IEEE International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353595
  28. Milova Paul, B. Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Contact and Junction Engineering in Bulk FinFET Technology for Improved ESD/Latch-up Performance with Design Trade-offs and Its Implications on Hot Carrier Reliability”, 56th IEEE International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353573
  29. Bhawani Shankar, Ankit Soni, Sayak Dutta Gupta, R. Sengupta, H. Khand, N. Mohan, Srinivasan Raghavan and Mayank Shrivastava, “On the Trap Assisted Stress Induced Safe Operating Area Limits of AlGaN/GaN HEMTs”, 56th IEEE International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353596
  30. N. K. Kranthi, Abhishek Mishra, Adil Meersha, Harsha B. Variar and Mayank Shrivastava, “Defect-Assisted Safe Operating Area Limits and High Current Failure in Graphene FETs”, 56th IEEE International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353571
  31. Rajat Sinha, Prasenjit Bhattacharya, Sanjiv Sambandan and Mayank Shrivastava, “On the ESD Behavior of a-Si:H based Thin-Film Transistors: Physical Insights, Design and Technological Implications”, 56th IEEE  International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353572
  32. Sampath Kumar B, Milova Paul, Harald Gossner and Mayank Shrivastava, “Performance and Reliability Insights of Drain Extended FinFET Devices for High Voltage SoC Applications”, 30th Int’l Symposium on Power Semiconductor Devices and ICs (ISPSD), Chicago, USA, May 13-17, 2018. DOI: 10.1109/ISPSD.2018.8393605
  33. Karmel Kranthi Nagothu, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “On the ESD Reliability issues in Carbon electronics: Graphene and Carbon Nano Tubes”, 31st International Conference on VLSI Design (VLSID), Jan 2018. DOI: 10.1109/VLSID.2018.117
  34. Vipin Joshi, Bhawani Shankar, Shree Prakash Tiwari and Mayank Shrivastava, “Dependence of Avalanche Breakdown on Surface & Buffer Traps in AlGaN/GaN HEMTs”, 22nd IEEE SISPAD, Japan, September 7-9, 2017 DOI: 10.23919/SISPAD.2017.8085276
  35. B. Sampath Kumar, Milova Paul and Mayank Shrivastava, “On the Design Challenges of Drain Extended FinFETs for Advance SoC Integration”, 22nd IEEE SISPAD, Japan, September 7-9, 2017 DOI: 10.23919/SISPAD.2017.8085296
  36. Adil Meersha, Harsha B Variar, Krishna Bharadwaj, Abhishek Mishra, Srinivasan Raghavan, Navakanta Bhat and Mayank Shrivastava, “Record Low Metal – (CVD) Graphene Contact Resistance Using Atomic Orbital Overlap Engineering”, Proceedings of IEEE International Electron Device Meeting, Dec. 5th – Dec. 7th, San Francisco, CA, USA, 2016 DOI: 10.1109/IEDM.2016.7838352
  37. N. K. Kranthi, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “ESD Behavior of Large Area CVD Graphene RF Transistors: Physical Insights and Technology Implications”, Proceedings of 55th IEEE International Reliability Physics Symposium (IRPS), USA, April 4th – April 6th, 2017  DOI: 10.1109/IRPS.2017.7936298
  38. Bhawani Shankar, Ankit Soni, Manikant Singh, Rohith Soman, Hareesh Chandrasekar , Nagaboopathy Mohan, Neha Mohta, Nayana Ramesh, Shreesha Prabhu, Abhay Kulkarni, Digbijoy Nath, R. Muralidharan, K. N. Bhat, Srinivasan Raghavan, Navakant Bhat and Mayank Shrivastava, “Trap Assisted Avalanche Instability and Safe Operating Area Concerns in AlGaN/GaN HEMTs”, Proceedings of 55th IEEE International Reliability Physics Symposium (IRPS), USA, April 4th – April 6th, 2017 DOI: 10.1109/IRPS.2017.7936414
  39. Milova Paul, B. Sampath Kumar, Christian Russ, Harald Gossner and Mayank Shrivastava, “FinFET SCR: Design Challenges and Novel Fin SCR Approaches for On-Chip ESD Protection”, Proceedings of 39th EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA DOI: 10.23919/EOSESD.2017.8073437
  40. Bhawani Shankar, Rudrarup Sengupta, Sayak Dutta Gupta, Ankit Soni, Nagaboopathy Mohan, Navakant Bhat, Srinivasan Raghavan and Mayank Shrivastava, “On the ESD Behavior of AlGaN/GaN Schottky Diodes and Trap Assisted Failure Mechanism”, Proceedings of 39th EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA DOI: 10.23919/EOSESD.2017.8073423
  41. Rajat Sinha, N.K. Kranthi, Sanjiv Sambandan and Mayank Shrivastava, “On the ESD Behavior of Pentacene Channel Organic Thin Film Transistor”, Proceedings of 39th EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA DOI: 10.23919/EOSESD.2017.8073426
  42. Abhishek Mishra and Mayank Shrivastava, “Unique Current Conduction Mechanism through Multi Wall CNT Interconnects under ESD Conditions”, Proceedings of 38th EOSESD Symposium, Anaheim, CA, USA, 11th – 14th September, 2016 DOI: 10.1109/EOSESD.2016.7592528
  43. Abhishek Mishra and Mayank Shrivastava, “New Insights on the ESD Behavior and Failure Mechanism of Multi Wall CNTs”, Proceedings of 54th IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, USA, 17th – 19th April, 2016 DOI: 10.1109/IRPS.2016.7574609
  44. Bhawani Shankar and Mayank Shrivastava, “Unique ESD Behavior and Failure Modes of AlGaN/GaN HEMTs”, Proceedings of 54th IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, USA, 17th – 19th April, 2016 DOI: 10.1109/IRPS.2016.7574608
  45. Milova Paul, Christian Russ, B Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete?”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017 (Received outstanding research paper award) DOI: 10.1109/VLSID.2017.32
  46. Bhawani Shankar and Mayank Shrivastava, “ESD Behavior of AlGaN/GaN HEMT on Si: Physical Insights, Design Aspects, Cumulative Degradation and Failure Analysis”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017 DOI: 10.1109/VLSID.2017.57
  47. Adil Meersha, Sathyajit B and Mayank Shrivastava, “A Systematic Study on the Hysteresis Behavior and Reliability of MoS2 FET”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017 DOI: 10.1109/VLSID.2017.67
  48. Peeyusha S. Swain, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “Device-Circuit Co-design for High Performance Level Shifter by Limiting Quasi-saturation Effects in Advanced DeMOS Transistors”, IEEE INEC, 9th – 11th, May, 2016, China DOI: 10.1109/INEC.2016.7589264
  49. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology mounted in BGA Package”, Proceedings of IEEE VLSI Design Conference, Jan. 2016 DOI: 10.1109/VLSID.2016.30
  50. Ketankumar Tailor, Mayank Shrivastava, Harald Gossner, Maryam Baghini, Ramgopal Rao, “On the Breakdown Physics of Trench-Gate Drain Extended NMOS”, Proceedings of IEEE Electron Devices and Solid-State Circuits Conference, June 2015, Singapore. DOI: 10.1109/EDSSC.2015.7285240
  51. Ketankumar Tailor, Mayank Shrivastava, Harald Gossner, Maryam Baghini, Ramgopal Rao, “Comparison of Breakdown Characteristics of DeNMOS Devices with Various Drain Structures”, Proceedings of IEEE Electron Devices and Solid-State Circuits Conference, June 2015, Singapore. DOI: 10.1109/EDSSC.2015.7285222
  52. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Drain Extended MOS Device Design for Integrated RF PA in 28nm CMOS with Excellent FoM and ESD Robustness”, Proceeding of IEEE International Electron Device Meeting (IEDM) Dec. 2014, San Francisco, CA, USA. DOI: 10.1109/IEDM.2014.7046974
  53. Mayank Shrivastava and Harald Gossner, “ESD Behavior of Metallic Carbon Nanotubes”, Proceedings of 36th EOSESD Symposium, 7th – 12th Sep. 2014, Tucson, Arizona, USA. INSPEC Accession Number: 14789864
  54. Mayank Shrivastava, Christian Russ, Harald Gossner, S. Bychikhin, D. Pogany and E. Gornik, “ESD Robust DeMOS Devices in Advanced CMOS Technologies”, Proceedings of EOSESD symposium, 11th – 15th Sep. 2011, Anaheim, California, USA. NSPEC Accession Number: 12316388
  55. Junjun Li, Rahul Mishra, Mayank Shrivastava, Yang Yang, Robert Gauthier, Christian Russ, “Technology Scaling Effects of Silicide-blocked PMOSFET Devices under ESD like conditions in Advanced Nanometer Node Bulk CMOS Technologies”, Proceedings of EOSESD Symposium, 11-15 Sep. 2011, Anaheim, California, USA INSPEC Accession Number: 12316385.
  56. Mayank Shrivastava, Manish Agrawal, Jasmin Aghassi, Harald Gossner, Wolfgang Molzer, Thomas Schulz, V. Ramgopal Rao, “On the thermal failure in nanoscale devices: Insight towards Heat Transport and Design Guidelines for Robust Thermal Management & EOS/ESD Reliability”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), 10-14 April, 2011, Monterey, CA, USA. DOI: 10.1109/IRPS.2011.5784498
  57. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini and V. Ramgopal Rao, “On the Transient Behavior of Various Drain Extended MOS Devices under the ESD stress conditions”, Proceedings of 7th International SoC Design Conference (ISOCC 2010), November 22-23, 2010, Songdo Convensia, Incheon, Korea (Invited) DOI: 10.1109/SOCDC.2010.5682922
  58. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini and V. Ramgopal Rao, “3D TCAD based approach for the Evaluation of Nanoscale Devices during ESD Failure”, Proceedings of 7th International SoC Design Conference (ISOCC 2010), November 22-23, 2010, Songdo Convensia, Incheon, Korea (Invited) DOI: 10.1109/SOCDC.2010.5682919
  59. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “On the failure mechanism and current instabilities in RESURF type DeNMOS device under ESD conditions”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), May 2nd – 6th, 2010, Anaheim, California, USA. DOI: 10.1109/IRPS.2010.5488723
  60. Mayank Shrivastava, S. Bychikhin, D. Pogany, Jens Schneider, M. Shojaei Baghini, Harald Gossner, Erich Gornik, V. Ramgopal Rao, “On the differences between 3D filamentation and failure of n & p type drain extended MOS devices under ESD condition”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), May 2nd – 6th, 2010, Anaheim, California, USA. DOI: 10.1109/IRPS.2010.5488785
  61. Mayank Shrivastava, Bhaskar Verma, M. Shojaei Baghini, Christian Russ, Dinesh K. Sharma, Harald Gossner, V. Ramgopal Rao, “Benchmarking the Device Performance at sub 22 nm node Technologies using an SoC Framework”, Proceedings of IEEE International Electron Device Meeting (IEDM), 7th -9th Dec, 2009, Baltimore, USA. DOI: 10.1109/IEDM.2009.5424311
  62. Mayank Shrivastava, S. Bychikhin, D. Pogany, Jens Schneider, M. Shojaei Baghini, Harald Gossner, Erich Gornik, V. Ramgopal Rao, “Filament Study of STI type Drain extended NMOS device using Transient Interferometric Mapping”, Proceedings of IEEE International Electron Device Meeting (IEDM), 7th -9th Dec, 2009, Baltimore, USA. DOI: 10.1109/IEDM.2009.5424337
  63. Mayank Shrivastava, Jens Schneider, Ruchil Jain, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “IGBT plugged in SCR device for ESD protection in advanced CMOS technology”, Proceedings of EOS/ESD symposium, August 30th – September 4th, 2009, Anaheim, CA, USA. INSPEC Accession Number: 10980103
  64. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “Highly resistive body STI: n-DEMOS: An optimized DEMOS device to achieve moving current filaments for robust ESD protection”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), April 26th – 30th, 2009, Montreal, Quebec, Canada. DOI: 10.1109/IRPS.2009.5173344
  65. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “A New Physical Insight and 3D Device Modeling of STI Type DENMOS Device Failure under ESD Conditions”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), April 26th – 30th, 2009, Montreal, Quebec, Canada. DOI: 10.1109/IRPS.2009.5173327

Other Peer Reviewed International Conferences

  1. Vipin Joshi, Sayak Dutta Gupta, Rajarshi Roy Chaudhuri, and Mayank Shrivastava, “Unique C-doped GaN Buffer Transport Dependence of Breakdown Voltage in Normally-OFF Cascode HEMTs,” 2022 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2022.
  2. S. K. Gautam, Jatin, M. Monishmurali, and Mayank Shrivastava, “The Physical Insight into Holding Voltage Engineering of SCR for ESD Protection,” 2022 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2022.
  3. Jatin, S. K. Gautam, M. Monishmurali, and Mayank Shrivastava, “Performance and Reliability Co-Design of HV devices in Vertically Stacked Nanosheet Technology,” 2022 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2022.
  4. Utpreksh Patbhaje, Rupali Verma, and Mayank Shrivastava, “Unique Reliability Concern on Intrinsic MoSe2 FET Channel”, to appear in Graphene Week 2022, Munich, Germany, September 5-9, 2022
  5. Jeevesh Kumar, Utpreksh Patbhaje, and Mayank Shrivastava, “Atomic-level investigation to resolve performance and reliability bottlenecks of the 2D material devices for the electronic application”, to appear in Graphene Week 2022, Munich, Germany, September 5-9, 2022
  6. Rupali Verma, Utpreksh Patbhaje, and Mayank Shrivastava, “Effect of in-plane electric field on the excitonic photoluminescence quenching and photocurrent generation in monolayer WS2”, to appear in Graphene Week 2022, Munich, Germany, September 5-9, 2022
  7. Anand Kumar Rai and Mayank Shrivastava, “Plasma and Pulse Stress Combined Flawless Effect for Performance Boosting of MoS2 FETs”, to appear in Graphene Week 2022, Munich, Germany, September 5-9, 2022
  8. Rajarshi Roy Chaudhuri, Vipin Joshi, Sayak Dutta Gupta, and Mayank Shrivastava, “Hot Electron Interaction with C-doped GaN buffer and Resultant Gate Leakage Degradation in AlGaN/GaN HEMTs,” GaN Marathon 2022, Venice, Italy, June 20-22, 2022
  9. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri, and Mayank Shrivastava, “Physics-Based Approach for Mitigation of Dynamic RON in AlGaN/GaN HEMTs with C-doped buffer,” GaN Marathon 2022, Venice, Italy, June 20-22, 2022
  10. Mayank Shrivastava, “Reliable Enhancement-Mode AlGaN/GaN HEMTs by p-type AlTiO Based Gate Stack Engineering,” GaN Marathon 2022, Venice, Italy, June 20-22, 2022
  11. Rajarshi Roy Chaudhuri, Vipin Joshi, Sayak Dutta Gupta and Mayank Shrivastava, “Experimental Observations of Hot Electron Interaction with Traps in C-doped GaN buffer in AlGaN/GaN HEMTs: Investigating the Role of Lateral Electric Field”, GaN Marathon 2020, Padua, Italy, April 2020
  12. Sayak Dutta Gupta, Vipin Joshi, Rajarshi Roy Chaudhuri, and Mayank Shrivastava, ” Physical insights into Dynamic RON in AlGaN/GaN HEMTs with carbon-doped buffer”, GaN Marathon 2020, Padua, Italy, April 2020
  13. Gaurav Sheoran, Jeevesh Kumar, Ansh, Srinivasan Raghavan and Mayank Shrivastava, “Universal approach to achieve enhanced ambipolar behaviour in all TMDs and CVD monolayer MoS2 based Field Effect Transistors (FETs)”, Graphene 2019, Rome, Italy, June 2019.
  14. Ansh, Jeevesh Kumar, Ravi K Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Chalcogen assisted contact engineering: towards CMOS circuit integration of WSe2 FETs”, Graphene 2019, Rome, Italy, June 2019.
  15. Harsha Variar, Jeevesh Kumar, Ansh, Srinivasan Raghavan and Mayank Shrivastava, “Overall performance improvement of Transition Metal Dichalcogenides (TMDs) based Field-Effect Transistors (FETs) via Chalcogen assisted channel and contact engineering”, Graphene 2019, Rome, Italy, June 2019.
  16. Jeevesh Kumar, Ansh, Adil Meersha and Mayank Shrivastava, “A deep Insight into Defect Engineering at the Metal-Graphene and Metal-Phosphorene Interfaces”, Graphene 2019, Rome, Italy, June 2019.
  17. Hemanjaneyulu Kuruva, Jeevesh Kumar and Mayank Shrivastava, “Improving the efficiency of MoS2 based FETs through Potassium Iodide doping”, Graphene 2019, Rome, Italy, June 2019.
  18. Ansh, Jeevesh Kumar, Gaurav Sheoran, Ravi K Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Chalcogen assisted contact engineering: a universal approach to realize enhanced hole injection across CVD TMD monolayer – metal interfaces”, to appear in Graphene Week 2019, Finland, September 2019.
  19. Ansh, Jeevesh Kumar, Ravi K Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Chalcogen assisted contact engineering led unique MIGS and DIGS at WSe2-metal interface enabling CMOS circuit integration of WSe2 transistors”, to appear in Graphene Week 2019, Finland, September 2019.
  20. Jeevesh Kumar, Ansh, Adil Meersha and Mayank Shrivastava, “A First Principle Insight into Defect Engineering at the Metal-Graphene and Metal-Phosphorene Interfaces”, to appear in Graphene Week 2019, Finland, September 2019.
  21. Jeevesh Kumar, Ansh and Mayank Shrivastava, “A First Principle Insight into Defect Assisted Band Gap Creation in Graphene”, to appear in Graphene Week 2019, Finland, September 2019.
  22. Abhishek Mishra, Adil Meersha, V Bellamkonda, G Sheoran, A Rao, Srinivasan Raghavan, Mayank Shrivastava, Investigation of Time-evolution of Electro-thermal Transport through Graphene-based Transistors and its Impact on the Device Reliability, to appear in Graphene Week 2019, Finland, September 2019.
  23. B. Shankar, A. Soni, S. Dutta Gupta, R. Sengupta, H. Khand, N. Mohan, S. Raghavan, N. Bhat, and Mayank Shrivastava, “Design and Reliability of GaN Power HEMT Technology”, AiMES 2018 Meeting (September 30 – October 4, 2018) (Invited) http://ma.ecsdl.org/content/MA2018-02/16/713.short
  24. Mayank Shrivastava, Christian Russ, Harald Gossner, “On the Impact of ESD Implant and Filament Spreading in Drain extended NMOS devices”, International ESD Workshop, May 2011, Lake Tahoe, CA, USA.
  25. A. B. Sachid, Mayank Shrivastava, R. A. Thakkar, M. Shojaei Baghini, D. K. Sharma, M. B. Patil, V. Ramgopal Rao, “Technology-Aware Design (TAD) for Sub-45nm CMOS Technologies”, Intel Asia Academic Forum 2008, Oct. 20th – Oct. 22nd 2008, Taipei, Taiwan. (Received the best research paper award).
  26. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Reliability aware I/O design for sub 45nm node CMOS technology”, IWPSD-2009, 15th -19th Dec, 2009 (Invited).

Job Title: Program Manager

Applications are invited for a full-time position as the Program Manager (PM)

Essential Qualifications: Doctorate in  any science and engineering discipline, preferably physics/nanoscience/semiconductors.

Preference: Knowledge of semiconductors/solid state physics/nanoscience-related disciplines/topics and research management experience will be preferred. The candidate should have excellent oral and written communication skills. The candidate must be proficient in soft skills such as Advance features of tools such as Outlook, PowerPoint Presentation, MS Word, MS Excel, and possibly project Libre. Besides, the candidate must have excellent management skills, such as the capability to manage multiple things at a time, keep track of timelines and deadlines, and have skills to get the job done, other than convincing and negotiation ability.

Age: 25 to 35 years

Remuneration:  The  salary  will  be  fixed  within  INR  70,000  to  80,000/  per  month  (consolidated)  based  on  the candidate’s qualifications, experience, and suitability. The position is full-time, temporary, and contractual.

Job Location: Indian Institute of Science, Bangalore.

Job Description:

  • Scientific & Technical management of MSDLab
    • R&D Project management: Communication with collaborators, government funding bodies, finance, and legal teams for smooth execution of projects. Scheduling weekly/monthly project reviews, MoMs & annual reports documentation.
    • Outreach: Coordination with lab members (past & present) for research articles, presentations & videos, etc; ideation & execution for promoting MSDLab research activities through social media.
    • To  negotiate and execute legal agreements  like MoUs, NDA, and  R&D  contracts  between industry  & academic collaborators.
    • Interviews:  Data  collection  of  candidates,  scheduling  interviews,  facilitating  the  onboarding  activities, communication-related to internships, postdoc fellowships, etc.
    • Managing alumni database, tracking student-related research activities
    • Coordination with Sponsors, Project collaborators, etc.
    • Purchase: Domestic and Global tender processing, laboratory inventory management, liaising with logistics.
    • Travel planning and management
  • To manage tasks related to a  larger initiative in terms of collecting  MoM,  helping with market research, coordinating with industry/academia and investigators from other institutes, compiling reports/proposals, etc.
  • Managing activities under IEEE Head
    • Facilitate conference/workshop planning and management, liaise with funding agencies, sponsors, conference delegates, and participants to coordinate the event
    • IEEE EDS/SSCS Bangalore Chapter activities: Managing and coordinating weekly talks, Distinguished Lecturers, Mini Colloquim, reporting, outreach, broadcasting, sponsorships, etc.
  • Outreach and funding drive for the M-Tech Microelectronics program: working on websites/SM platforms, hosting sessions with GATE aspirants, and connecting with the industry with our help to raise sponsorships and funds under CSR.

Besides, the PM may need to coordinate or help manage new initiatives/degree programs, etc.

Interested candidates may fill out the online form and send your max.  4-page CV  (pdf only, max 5 MB size)  msdlab.ese@iisc.ac.in on/before Wednesday, 30th November 2022, 11:55 PM. Short-listed candidates will be called for an online interview.